Datasheet

TPS77301/315/316/318/327/328/333/350 WITH RESET OUTPUT
TPS77401/415/418/427/428/433/450 WITH POWER GOOD OUTPUT
250-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING
SLVS281E – FEBRUARY 2000 – REVISED JULY 2001
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
TPS773XX
FB/SENSE 1 I Feedback input voltage for adjustable device (sense input for fixed options)
RESET 2 O Reset output
EN 3 I Enable input
GND 4 Regulator ground
IN 5, 6 I Input voltage
OUT 7, 8 O Regulated output voltage
TPS774XX
FB/SENSE 1 I Feedback input voltage for adjustable device (sense input for fixed options)
PG 2 O Power good
EN 3 I Enable input
GND 4 Regulator ground
IN 5, 6 I Input voltage
OUT 7, 8 O Regulated output voltage
TPS773xx RESET timing diagram
†
V
res
is the minimum input voltage for a valid RESET
. The symbol V
res
is not currently listed within EIA or JEDEC standards for semiconductor
symbology.
V
I
V
res
†
t
t
t
V
O
Threshold
Voltage
RESET
Output
220 ms
Delay
220 ms
Delay
Output
Undefined
Output
Undefined
V
IT+
‡
V
IT–
‡
V
IT–
‡
V
IT+
‡
‡
V
IT
– Trip voltage is typically 5% lower than the output voltage (95%V
O
) V
IT–
to V
IT+
is the hysteresis voltage.
V
res
†