Datasheet

Low Dropout Voltage Linear Regulator Circuit Operation
1-2
1.1 Low Dropout Voltage Linear Regulator Circuit Operation
In the low dropout voltage linear regulator topology, a PMOS transistor acts as
a pass element that reduces the normal 1.5-V to 2.5-V collector-to-emitter
drop to about 0.3 V or less. This improvement results in lower power
dissipation and higher efficiency when compared to other regulator designs.
The basic LDO regulator circuit includes the LDO and an output capacitor for
stabilization. Figure 1–1 shows the circuit of a typical LDO application.
Figure 1–1. Typical LDO Application
_
+
Control
_
+
R1
R2
Q1
V
ref
LDO
C
O
V
out
Load
_
+
V
CC
In the LDO application shown in Figure 1–1, the LDO regulates the output
voltage V
out
.
If V
out
falls below the regulation level, the controller increases the V
GS
differential and the PMOS conducts more current, resulting in an increase of
V
out
. If V
out
exceeds the regulation level, the controller decreases the V
GS
differential and the PMOS conducts less current, resulting in a decrease of
V
out
. The PMOS pass element acts like an adjustable resistor. The more
negative the gate becomes versus the source, the less the source-drain
resistance becomes, resulting in higher current flow through the PMOS.