LDO Linear Regulator Design Using the Universal SOT23 EVM User’s Guide August 1999 Mixed Signal Products SLVU019
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Information About Cautions and Warnings Preface Read This First About This Manual This user’s guide describes techniques for designing low dropout voltage linear regulators (LDO) using TI’s SLVP125 evaluation modules (EVM) and TPS 76933 LDOs.
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Running Title—Attribute Reference Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Low Dropout Voltage Linear Regulator Circuit Operation . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Design Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . .
Running Title—Attribute Reference Figures 1–1 1–2 1–3 1–4 1–5 2–1 2–2 3–1 3–2 3–3 3–4 3–5 3–6 4–1 4–2 4–3 4–4 4–5 4–6 4–7 Typical LDO Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLVP125 EVM Universal LDO Tester Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1 Introduction This user’s guide describes techniques for designing low dropout (LDO) voltage linear regulators using TI’s SLVP125 evaluation module (EVM) and TPS76933 LDO. LDOs provide ideal power supplies for rapidly transitioning DSP loads such as the Texas Instruments TMS320C54x and similar processors, and fast memory.
Low Dropout Voltage Linear Regulator Circuit Operation 1.1 Low Dropout Voltage Linear Regulator Circuit Operation In the low dropout voltage linear regulator topology, a PMOS transistor acts as a pass element that reduces the normal 1.5-V to 2.5-V collector-to-emitter drop to about 0.3 V or less. This improvement results in lower power dissipation and higher efficiency when compared to other regulator designs. The basic LDO regulator circuit includes the LDO and an output capacitor for stabilization.
Design Strategy 1.2 Design Strategy The TI SLVP125 EVM provides a circuit to simultaneously compare the performance of two LDOs in a SOT23 package. The EVM provides proven, demonstrated reference designs and test modes to aid in choosing and evaluating LDOs. A programmable high speed transient generator generates either line or load transients. The transient slew rate, and the impact of the transients on the load/line are adjustable.
Schematic 1.3 Schematic Figure1–2 shows the SLVP125 EVM Universal LDO Tester (3.3 V output with TPS76933 as U1) schematic diagram. Figure 1–2.
Schematic Figure 1–2.
Bill of Materials 1.4 Bill of Materials Table 1–2 lists materials required for the SLVP125 EVM. Table 1–2. SLVP125 EVM Bill of Materials Ref PN Description Mfg Size C1 16SA470M Capacitor, OS-Con, 470 µF, 16 V, 20-mΩ, 20% Sanyo G C1 (Alt) 16SP470M Capacitor, OS-Con, 470 µF, 16 V, 10-mΩ, 20% Sanyo G C2 ECU-V1H104KBW Capacitor, ceramic, 0.
Bill of Materials Table 1–2. SLVP125 EVM Bill of Materials (Continued) Ref PN Description R10 Std Resistor, Chip, user option, 1/8 W, 1% Mfg Size 1206 R11 Std Resistor, chip, 10.0 MΩ, 1/8 W, 1% R12 72-T93YA-10 Trim Pot, cermet, 10 Ω vertical, top adjust, 1/2 W, 10% 1206 R13 Std Resistor, chip, user option, 1/8-1 W, 1% R14 Std Resistor, CF, 5.
Board Layout 1.5 Board Layout Figures 1–3 through 1-6 show the board layout for the SLVP125 EVM. Figure 1–3. Top Layer Figure 1–4.
Board Layout Figure 1–5.
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Chapter 2 EVM Adjustments and Test Points This chapter explains the following four EVM adjustment modes: - Adjustment by switch Adjustment by jumper Adjustment by trimmer Adjustment by programming header Figure 2–1 shows the locations of the adjustment points on the board. Topic Page 2.1 Adjustment by Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2 2.2 Adjustment by Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adjustment by Switch 2.1 Adjustment by Switch - S1 toggles between high (direction labelling) or low transient generator frequency. S2 switches the transient generator on (direction labelling) and off. S3 toggles between slower (direction labelling) and faster transients. S4 directs transients either to DUT1 (direction labelling) or DUT2. 2.2 Adjustment by Jumper Table 2–1 lists adjustments that can be made by jumpers. Table 2–1.
Test Setup Table 2–3. Timing Equations Timing Equations With Diode DH1 for Low Duty Cycles RH1 RH2 Note: + 0.693ton t on + 0.693 C (1–D) D C Timing Equations Without Diode RH1 t on + 0.693 RH2 t on + 0.693 (2D–1) D C (1–D) D C ton = desired load on-time [s] D = on-time duty cycle C = total capacitance in circuit (CH1 or CH1 + CH2) [F] RH1, RH2 = Timer resistors value (refer to schematics) [Ω] Figure 2–1.
Test Setup 3) Connect a 2nd lab power supply (at least capable to supply 2 A) to the J1 and J3 connector at Vin and GND. The polarity is printed on the board. Verify that the output voltage limit is set to 13.5 V and that the output is set to 0 V. 4) Turn on the 12-V lab supply. Turn on the second power supply and ramp the input voltage up to the desired maximum but not further than 13.5 V. 5) Verify that the output voltage (measured at the Vout1 and Vout2 pins respectively) has the desired value.
Chapter 3 Circuit Design This chapter describes the LDO circuit design procedure. Topic Page 3.1 Adjusting the TPS76xx01/TPS77001 Output Voltage . . . . . . . . . . . . . 3–2 3.2 Temperature Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6 3.3 External Capacitor Requirements – ESR . . . . . . . . . . . . . . . . . . . . . . . .
Adjusting the TPS76x01/TPS77001 Output Voltage 3.1 Adjusting the TPS76x01/TPS77001 Output Voltage All voltage regulators of the TPS76x01/TPS77001 families use the same internal bandgap voltage, see also Figure 1–1. In the adjustable version, the resistors R1 and R2 are external resistors. Due to the virtual short circuit between the input pins of an op amp, the voltage Vref applies to both the +input pin and the –input pin.
Adjusting the TPS76x01/TPS77001 Output Voltage Figure 3–2. Resistor Values 1800 10 9 1600 max Value for R1+R2[kΩ] R1/R2 8 7 1200 6 1000 5 800 4 Resistor ratio R1/R2 max. Value for R1 + R2 – kΩ 1400 600 3 400 2 12 11.2 11.6 10.8 10 10.4 8.8 9.2 9.6 8 8.4 7.6 6 6.4 6.8 7.2 5.6 4.8 5.2 4 4.4 3.6 3.2 2.8 0 2.4 0 1.6 2 1 1.2 200 Output Voltage [V] Table 3–1. Exact Resistor Values Vout R1/R2 Maximum Value for R1+R2[kΩ] 1.2 0.018676 171.429 1.3 0.103565 185.714 1.4 0.
Adjusting the TPS76x01/TPS77001 Output Voltage Table 3–1. Exact Resistor Values(Continued) Vout R1/R2 Maximum Value for R1+R2[kΩ] 3.4 1.886248 485.714 3.5 1.971138 500.000 3.6 2.056027 514.286 3.7 2.140917 528.571 3.8 2.225806 542.857 3.9 2.310696 557.143 4 2.395586 571.429 4.1 2.480475 585.714 4.2 2.565365 600.000 4.3 2.650255 614.286 4.4 2.735144 628.571 4.5 2.820034 642.857 4.6 2.904924 657.143 4.7 2.989813 671.429 4.8 3.074703 685.714 4.9 3.159593 700.
Adjusting the TPS76x01/TPS77001 Output Voltage For 3 V, one gets: + 1.546689 II) R1 ) R2 + 428.571 kW å IȀ) R1 + 1.546689 R2 IȀ) in II) : å 1.546689 R2 ) R2 + 428.571 kW kW + 168.286 kW å R2 + 428.571 2.546689 I) R1 R2 Make R2 = 169 kΩ and calculate R1: Derived from equation I), one gets for R1: R1 + 1.546689 W + 261.39 kW 169 k The next value in the E96 series shown in Table 3–2 is 261 kΩ. ǒ The error for using these resistors is: W + 1.544379 å Error + 261 k 169 kW 1– 1.544379 1.
Temperature Considerations 3.2 Temperature Considerations To protect the device and assure the specifications, the maximum junction temperature should not exceed 125°C. This restriction limits the power dissipation the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or equal to PD(max).
External Capacitor Requirements – ESR Figure 3–3. Calculated and Measured Maximum Output Current vs Input Voltage Without Cooling for TPS76933 in Test Setup 350 3.4 ±3% Vout – Tolerance Area 300 mA Current limit 300 3.2 Iout, max vs. Input Voltage, calculated Values 250 3 Vout at Iout, max 200 2.8 Vout [V] I out [mA] Iout, max vs. Input Voltage, measured Values Vout at Iout = 100 mA 150 2.6 100 2.4 50 2.2 0 2 3 4 5 6 7 8 9 10 11 12 13 14 Vin [V] 3.
External Capacitor Requirements – ESR Figure 3–5. LDO Output Stage With Parasitic Resistances ESR and ESL Iout LDO RESR VESR Vin LESL VCout RLOAD Vout Cout In steady state (dc state condition) the load is supplied by the LDO (solid arrow) and VCout = Vout. This means no current is flowing into the Cout branch.
External Capacitor Requirements – ESR Figure 3–6. Correlation of Different ESRs and Their Influence to the Regulation of Vout at a Load Step From Low to High Output Current Iout Vout 1 2 ESR 1 3 ESR 2 ESR 3 tL t1 t2 In order to get a good performing system, an LDO with short response time and an output capacitor with low ESR are required. For any regulator of the TPS76xxx/TPS770xx series, an output capacitor of at least 4.7 µF is required. The ESR of the capacitor should be between 0.
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Chapter 4 Test Results This chapter presents laboratory test results for the LDO design. Topic 4.
Test Results 4.1 Test Results Figures 4–1 through 4–7 show the results of various tests and test conditions for the circuit using the TPS76933 device. Figure 4–1. Rise Time of Function Generator at Gate of MOSFET Q1 (high speed) Figure 4–2.
Test Results Figure 4–3. Transient at Input (Ch1); 4.3 V Input, 3.3 V Output (Ch2) at 100 mA Load, Cout = 10 µF Spike Output Voltage Figure 4–4.
Test Results Figure 4–5. Full Load (100 mA) – No Load Transition, ∆Vout , Whole Period Output Voltage (see Note 2) Load Transition (see Note 1) Figure 4–6.
Test Results Figure 4–7. No Load – Full Load (100 mA) Transition With Cout = 10 µF Electrolytic Output Voltage (see Note 2) Load Transition (see Note 1) Notes: 1) The load transition was measured as the voltage drop at the drain of Q1 (see Figure 1–2). Therefore load on is displayed as 0 V and load off is displayed as 3.3 V. 2) In order to display the output voltage transient with high resolution, a dc offset of 3.3 V was introduced. The actual dc values can be seen with the cursor lines in Figure 4–5.
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