Datasheet

TPS767D301-Q1, TPS767D318-Q1, TPS767D325-Q1
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
SGLS231A − FEBRUARY 2004 − JUNE 2008
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
1GND 3 Regulator #1 ground
1EN 4 I Regulator #1 enable
1IN 5, 6 I Regulator #1 input supply voltage
2GND 9 Regulator #2 ground
2EN 10 I Regulator #2 enable
2IN 11, 12 I Regulator #2 input supply voltage
2OUT 17, 18 O Regulator #2 output voltage
2RESET 22 O Regulator #2 reset signal
1OUT 23, 24 O Regulator #1 output voltage
1FB/NC 25 I Regulator #1 output voltage feedback for adjustable and no connect for fixed output
1RESET 28 O Regulator #1 reset signal
NC 1, 2, 7, 8,
13−16, 19, 20,
21, 26, 27
No connection
timing diagram
†
V
res
is the minimum input voltage for a valid RESET. The symbol V
res
is not currently listed within EIA or JEDEC standards
for semiconductor symbology.
V
I
V
res
†
V
res
t
t
t
V
O
Threshold
Voltage
RESET
Output
200 ms
Delay
200 ms
Delay
Output
Undefined
Output
Undefined
V
IT +
‡
V
IT −
V
IT −
V
IT +
‡
Less than 5% of the
output voltage
‡
VIT −Trip voltage is typically 5% lower than the output voltage (95%V
O
)