Datasheet

TPS767D301-Q1, TPS767D318-Q1, TPS767D325-Q1
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
SGLS231A − FEBRUARY 2004 − JUNE 2008
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
external capacitor requirements (continued)
When necessary to achieve low height requirements along with high output current and/or high ceramic load
capacitance, several higher ESR capacitors can be used in parallel to meet the previous guidelines.
RESET
OUT
OUT
6
5
4
IN
IN
EN
GND
3
28
24
23
V
I
C1
0.1 μF
50 V
RESET
V
O
10 μF
+
TPS767D3xx
C
O
250 kΩ
Figure 26. Typical Application Circuit (Fixed Versions) for Single Channel
programming the TPS767D301 adjustable LDO regulator
The output voltage of the TPS767D301 adjustable regulator is programmed using an external resistor divider
as shown in Figure 27. The output voltage is calculated using:
V
O
+ V
ref
ǒ
1 )
R1
R2
Ǔ
(1
)
where:
V
ref
= 1.1834 V typ (the internal reference voltage)
Resistors R1 and R2 should be chosen for approximately 50-μA divider current. Lower value resistors can be
used but offer no inherent advantage and waste more power. Higher values should be avoided as leakage
currents at FB increase the output voltage error. The recommended design procedure is to choose
R2 = 30.1 kΩ to set the divider current at 50 μA and then calculate R1 using:
R1 +
ǒ
V
O
V
ref
* 1Ǔ R2
(2)
OUTPUT
VOLTAGE
R1 R2
2.5 V
3.3 V
3.6 V
4 75V
UNIT
33.2
53.6
61.9
90.8
30.1
30.1
30.1
30.1
kΩ
kΩ
kΩ
kΩ
OUTPUT VOLTAGE
PROGRAMMING GUIDE
V
O
V
I
RESET
OUT
FB / NC
R1
R2
GND
EN
IN
<0.5V
>2.7 V
TPS767D301
RESET
Output
0.1 μF
250 kΩ
+
10 μF
C
O
Figure 27. TPS767D301 Adjustable LDO Regulator Programming