Datasheet

   
    
    
SGLS009B − MARCH 2003 − REVISED APRIL 2008
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing diagram
†
V
res
is the minimum input voltage for a valid RESET
. The symbol V
res
is not currently listed within EIA or JEDEC standards for semiconductor
symbology.
V
I
V
res
†
V
res
t
t
t
V
O
Threshold
Voltage
RESET
Output
200 ms
Delay
200 ms
Delay
Output
Undefined
Output
Undefined
V
IT+
‡
V
IT−
‡
V
IT−
‡
V
IT+
‡
Less than 5% of the
output voltage
‡
V
IT
−Trip voltage is typically 5% lower than the output voltage (95%V
O
) V
IT−
to V
IT+
is the hysteresis voltage.