Datasheet

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TPS759xx PG TIMING DIAGRAM
NOTE A: V
IT
–Trip voltage is typically 9% lower than the output voltage (91%V
O
) V
IT–
to V
IT+
is the hysteresis voltage.
t
t
t
Threshold
Voltage
PG
Output
V
IT+
(see Note A)
V
IN1
V
OUT
V
IT–
(see Note A)
V
UVLO
V
UVLO
DETAILED DESCRIPTION
PIN FUNCTIONS
Enable (EN)
Power-Good (PG)
Feedback (FB)
TPS75901, TPS75915
TPS75918, TPS75925, TPS75933
SLVS318E – DECEMBER 2000 – REVISED MARCH 2004
The TPS759xx family includes four fixed-output voltage regulators (1.5 V, 1.8 V, 2.5 V, and 3.3 V), and an
adjustable regulator, the TPS75901 (adjustable from 1.22 V to 5 V). The bandgap voltage is typically 1.22 V.
The EN terminal is an input which enables or shuts down the device. If EN is a logic high, the device will be in
shutdown mode. When EN goes to logic low, then the device will be enabled.
The PG terminal for the fixed voltage option devices is an open drain, active low output that indicates the status
of V
O
(output of the LDO). When V
O
reaches approximately 91% of the regulated voltage, PG will go to a low
impedance state. It will go to a high-impedance state when V
O
falls below 91% (i.e., over load condition) of the
regulated voltage. The open drain output of the PG terminal requires a pullup resistor.
FB is an input terminal used for the adjustable-output option and must be connected to the output terminal either
directly, in order to generate the minimum output voltage of 1.22 V, or through an external feedback resistor
divider for other output voltages. The FB connection should be as short as possible. It is essential to route it in
such a way to minimize/avoid noise pickup. Adding RC networks between FB terminal and V
O
to filter noise is
not recommended because it may cause the regulator to oscillate.
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