Datasheet

www.ti.com
THERMAL INFORMATION
P
D
max 

V
I(avg)
 V
O(avg)

 I
O(avg)
 V
I(avg)
x I
(Q)
(1)
A
B
C
A
B
C
T
J
A
R
θ
JC
T
C
B
R
θ
CS
T
A
C
R
θ
SA
(a)
(b)
TO–263 Package
TO–220 Package
TPS75901, TPS75915
TPS75918, TPS75925, TPS75933
SLVS318E – DECEMBER 2000 – REVISED MARCH 2004
The amount of heat that an LDO linear regulator generates is directly proportional to the amount of power it
dissipates during operation. All integrated circuits have a maximum allowable junction temperature (T
J
max)
above which normal operation is not assured. A system designer must design the operating environment so that
the operating junction temperature (T
J
) does not exceed the maximum junction temperature (T
J
max). The two
main environmental variables that a designer can use to improve thermal performance are air flow and external
heatsinks. The purpose of this information is to aid the designer in determining the proper operating environment
for a linear regulator that is operating at a specific power level.
In general, the maximum expected power (P
D(max)
) consumed by a linear regulator is computed as:
Where:
• V
I(avg)
is the average input voltage.
• V
O(avg)
is the average output voltage.
• I
O(avg)
is the average output current.
• I
(Q)
is the quiescent current.
For most TI LDO regulators, the quiescent current is insignificant compared to the average output current;
therefore, the term V
I(avg)
x I
(Q)
can be neglected. The operating junction temperature is computed by adding the
ambient temperature (T
A
) and the increase in temperature due to the regulator's power dissipation. The
temperature rise is computed by multiplying the maximum expected power dissipation by the sum of the thermal
resistances between the junction and the case (R
ΘJC
), the case to heatsink (R
ΘCS
), and the heatsink to ambient
(R
ΘSA
). Thermal resistances are measures of how effectively an object dissipates heat. Typically, the larger the
device, the more surface area available for power dissipation and the lower the object's thermal resistance.
Figure 21 illustrates these thermal resistances for (a) a TO-220 package attached to a heatsink, and (b) a
TO-263 package mounted on a JEDEC High-K board.
Figure 21. Thermal Resistances
14