Datasheet
SLVS293D − NOVEMBER 2000 − REVISED MAY 2002
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS755xx PG timing diagram
NOTE A: V
IT
−Trip voltage is typically 9% lower than the output voltage (91%V
O
). V
IT−
to V
IT+
is the hysteresis voltage.
t
t
t
Threshold
Voltage
PG
Output
V
IT+
(see Note A)
V
IN1
V
OUT
V
IT−
(see Note A)
V
UVLO
V
UVLO
detailed description
The TPS755xx family includes four fixed-output voltage regulators (1.5 V, 1.8 V, 2.5 V, and 3.3 V), and an
adjustable regulator, the TPS75501 (adjustable from 1.22 V to 5 V). The bandgap voltage is typically 1.22 V.
pin functions
enable (EN)
The EN
terminal is an input which enables or shuts down the device. If EN is a logic high, the device will be in
shutdown mode. When EN
goes to logic low, the device will be enabled.
power-good (PG
)
The PG
terminal for the fixed voltage option devices is an open drain, active low output that indicates the status
of V
O
(output of the LDO). When V
O
reaches approximately 91% of the regulated voltage, PG will go to a low
impedance state. It will go to a high-impedance state when V
O
falls below approximately 89% (i.e. over load
condition) of the regulated voltage. The open drain output of the PG
terminal requires a pullup resistor.
feedback (FB)
FB is an input terminal used for the adjustable-output option and must be connected to the output terminal either
directly, in order to generate the minimum output voltage of 1.22 V, or through an external feedback resistor
divider for other output voltages. The FB connection should be as short as possible. It is essential to route it in
such a way to minimize/avoid noise pickup. Adding RC networks between FB terminal and V
O
to filter noise is
not recommended because it may cause the regulator to oscillate.