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Conclusion
ESR 1
ESR 2
ESR 3
3
2
1
t
1
t
2
I
OUT
V
OUT
TPS751xxQ
TPS753xxQ
SLVS241C MARCH 2000 REVISED OCTOBER 2007
In steady state operation (dc state condition), the load current is supplied by the LDO (solid arrow) and the
voltage across the capacitor is the same as the output voltage (V(C
OUT
) = V
OUT
). This condition means that no
current is flowing into the C
OUT
branch. If I
OUT
suddenly increases (that is, a transient condition), the following
events occur:
The LDO is not able to supply the sudden current need because of its response time (t
1
in Figure 24 ).
Therefore, capacitor C
OUT
provides the current for the new load condition (the dashed arrow). C
OUT
now acts
like a battery with an internal resistance, ESR. Depending on the current demand at the output, a voltage
drop occurs at R
ESR
. This voltage is shown as V
ESR
in Figure 23 .
When C
OUT
is conducting current to the load, initial voltage at the load is V
OUT
= V(C
OUT
) V
ESR
. As a result
of the discharge of C
OUT
, the output voltage V
OUT
drops continuously until the response time t
1
of the LDO is
reached and the LDO resumes supplying the load. From this point, the output voltage starts rising again until
it reaches the regulated voltage. This period is shown as t
2
in Figure 24 .
Figure 24 also shows the impact of different ESRs on the output voltage. The left brackets show different levels
of ESRs where number 1 displays the lowest and number 3 displays the highest ESR.
From the above discussion, the following conclusions can be drawn:
The higher the ESR, the larger the droop at the beginning of load transient.
The smaller the output capacitor, the faster the discharge time and the bigger the voltage droop during the
LDO response period.
To minimize the transient output droop, capacitors must have a low ESR and be large enough to support the
minimum output voltage requirement.
Figure 24. Correlation of Different ESRs and Their Influence to the Regulation of V
OUT
at a Load Step
From Low-to-High Output Current
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