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V
IN
V
res
(1)
V
res
t
t
t
V
OUT
Threshold
Voltage
RESET
Output
100ms
Delay
100ms
Delay
Output
Undefined
Output
Undefined
V
IT+
(2)
Lessthan5%ofthe
OutputVoltage
V
IT+
(2)
V
IT-
(2)
V
IT-
(2)
V
IN
V
PG
(1)
V
PG
V
OUT
V
IT+
(2)
V
IT+
(2)
V
IT-
(2)
V
IT-
(2)
t
t
t
Output
Undefined
Output
Undefined
PG
Output
Threshold
Voltage
TPS751xxQ
TPS753xxQ
SLVS241C – MARCH 2000 – REVISED OCTOBER 2007
TPS753xxQ RESET Timing Diagram
(1) V
res
is the minimum input voltage for a valid RESET. The symbol V
res
is not currently listed within EIA or JEDEC
standards for semiconductor symbology.
(2) V
IT
: Trip voltage is typically 5% lower than the output voltage (95% V
OUT
). V
IT –
to V
IT+
is the hysteresis voltage.
TPS751xxQ Power Good Timing Diagram
(1) V
PG
is the minimum input voltage for a valid Power Good. The symbol V
PG
is not currently listed within EIA or JEDEC
standards for semiconductor symbology.
(2) V
IT
: Trip voltage is typically 17% lower than the output voltage (83% V
OUT
). V
IT –
to V
IT+
is the hysteresis voltage.
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