Datasheet

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100

150

0.3

Natural Convection

50 ft/min

250 ft/min

300ft/min

100 ft/min

150ft/min

200ft/min

R ThermalResistance

- -

C/W

CopperHeatsinkArea cm-

1 2

TPS751xxQ

TPS753xxQ

SLVS241C – MARCH 2000 – REVISED OCTOBER 2007

The PWP package is designed to optimize the heat transfer to the PWB. Because of the very small size and

limited mass of a TSSOP package, thermal enhancement is achieved by improving the thermal conduction paths

that remove heat from the component. The thermal pad is formed using a lead-frame design (patent pending)

and manufacturing technique to provide the user with direct connection to the heat-generating IC. When this pad

is soldered or otherwise coupled to an external heat dissipator, high power dissipation in the ultra-thin, fine-pitch,

surface-mount package can be reliably achieved.

Because the conduction path has been enhanced, power-dissipation capability is determined by the thermal

considerations in the PWB design. For example, simply adding a localized copper plane (heatsink surface) that is

coupled to the thermal pad enables the PWP package to dissipate 2.5 W in free air (see Figure 28 (a), 8 cm

copper heatsink and natural convection). Increasing the heatsink size increases the power dissipation range for

the component. The power dissipation limit can be further improved by adding airflow to a PWB/IC assembly

(see Figure 27 and Figure 28 ). The line drawn at 0.3 cm

in Figure 27 and Figure 28 indicates performance at

the minimum recommended heatsink size, illustrated in Figure 30 .

The thermal pad is directly connected to the substrate of the IC, which for the TPS751xxQPWP and

TPS753xxQPWP series is a secondary electrical connection to device ground. The heat-sink surface that is

added to the PWP can be a ground plane or left electrically isolated. In TO220-type surface-mount packages, the

thermal connection is also the primary electrical connection for a given terminal which is not always ground. The

PWP package provides up to 16 independent leads that can be used as inputs and outputs. (Note: leads 1, 10,

11, and 20 are internally connected to the thermal pad and the IC substrate.)

Figure 27. Thermal Resistance vs Copper Heatsink Area