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Power Dissipation and Junction Temperature
P =
D(Max)
T T
R
-
J(Max) A
JAq
(3)
P =(V V ) I-
D IN OUT OUT
´
(4)
THERMAL INFORMATION
Thermally-Enhanced TSSOP-20 (PWP – PowerPAD)
DIE
(a) Side View
(b) End View
(c) Bottom View
DIE
Thermal
Pad
TPS751xxQ
TPS753xxQ
SLVS241C – MARCH 2000 – REVISED OCTOBER 2007
Specified regulator operation is assured to a junction temperature of +125 ° C; the maximum junction temperature
should be restricted to +125 ° C under normal operating conditions. This restriction limits the power dissipation the
regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,
calculate the maximum allowable dissipation, P
D(max)
, and the actual dissipation, P
D
, which must be less than or
equal to P
D(max)
.
The maximum-power-dissipation limit is determined using Equation 3 :
where:
• T
J(max)
is the maximum allowable junction temperature
• R
θ JA
is the thermal resistance junction-to-ambient for the package; that is, 34.6 ° C/W for the 20-terminal PWP
with no airflow (see Dissipation Ratings Table ).
• T
A
is the ambient temperature
The regulator dissipation is calculated using Equation 4 :
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the thermal
protection circuit.
The thermally-enhanced PWP package is based on the 20-pin TSSOP, but includes a thermal pad [see
Figure 26 (c)] to provide an effective thermal contact between the IC and the printed wiring board (PWB).
Figure 26. Views of Thermally-Enhanced PWP Package
Traditionally, surface mount and power have been mutually exclusive terms. A variety of scaled-down
TO220-type packages have leads formed as gull wings to make them applicable for surface-mount applications.
These packages, however, suffer from several shortcomings: they do not address the very low profile
requirements (less than 2 mm) of many of today ’ s advanced systems, and they do not offer a pin-count high
enough to accommodate increasing integration. On the other hand, traditional low-power surface-mount
packages require power dissipation derating that severely limits the usable range of many high-performance
analog circuits.
The PWP package (a thermally-enhanced TSSOP) combines fine-pitch surface-mount technology with thermal
performance comparable to much larger power packages.
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