Datasheet
UVLO
TSD
UVLO
97%
TSD
BG
EN1
EN2
CL1
EN1
EN2
CL1
PD1
CL1
0.3 V
PG1
SW1
SW2
VS1
Delay
PD2
0.3 V
PG2
Delay
A
A
I > I ?
OUT1 CL1
CL2
I > I ?
OUT2 CL2
CT1CT2SS2 SS1GND
PD1
EN1
CL1
PG1
PD2
EN2
CL2
PG2
UVLO
TSD
SW1
SW2
Control
Logic
Sequencer
EN
SEQ
VMON
IN
VSET
VS1
PG
TEST
VDET
OUT1
OUT2
OUT1_S
OUT2_S
V
1.8 V/500 mA
CORE
V
3.3 V/500 mA
IO
110 pF
110 pF
2 pF2 pF
360 W
360 W
(Optional)
0.3 V
97%
97%
TPS75005
www.ti.com
SBVS144C –NOVEMBER 2011–REVISED APRIL 2012
FUNCTIONAL BLOCK DIAGRAM
Figure 1. Functional Block Diagram
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