Datasheet

NC
IN IN EN VMON
1
2
3
4
5
6
20
7
19
8
18
9
17
10
16
15
14
13
12
11
OUT2
OUT1
OUT1_S
CT1
SS1
TEST
GND GND
SEQ
VSET
PG
OUT2_S
CT2
SS2
VDET
TPS75005
SBVS144C –NOVEMBER 2011–REVISED APRIL 2012 www.ti.com
PIN CONFIGURATION
RGW PACKAGE
5-mm x 5-mm QFN-20
(TOP VIEW)
PIN DESCRIPTIONS
PIN
RGW
NAME QFN-20 DESCRIPTION
SVS1 internal-power-good delay setting. Leave this pin open for the default delay setting or connect capacitor
CT1 13
between this node and GND to program the delay. Do not connect a regular oscilloscope probe for monitoring.
SVS2 internal-power-good delay setting. Leave this pin open for the default delay setting or connect a capacitor
CT2 3
between this pin and GND to program the delay. Do not connect a regular oscilloscope probe for monitoring.
Enable inputs. Logic-H input to this pin triggers power-up sequence. Logic-L triggers power-down sequence.
EN 17 NOTE: The sequencing logic will automatically prevent powering up until the TPS75005 pulls the output rails to GND.
This ensures a proper startup every time.
GND 6, 7 Ground. Tie these pins to the thermal pad and maximize the copper in this area for optimal performance.
Power supply to the device. Connect a 10-µF X5R or X7R dielectric capacitor between IN and GND close to the
IN 18, 19
device.
NC 20 Not internally connected. This pin can be either tied to IN or GND to simplify layout.
OUT1 15 LDO1 output voltage. Connect a 10-µF X5R or X7R capacitor between this pin and ground close to the device.
OUT1_S 14 LDO1 output voltage sense input. Connect directly to output capacitor close to pin 15.
OUT2 1 LDO2 output voltage. Connect a 10-µF X5R or X7R capacitor between this pin and ground close to the device.
OUT2_S 2 LDO2 output voltage sense input. Connect directly to output capacitor close to pin 1.
Power-Good output. This is an open-drain output terminal and a pull-up resistor is required. The typical connection is
PG 10
100 kΩ to OUT2. When V
OUT1
> V
SVS1
and V
OUT2
> V
SVS2
, this pin outputs logic-H.
Sequence select pin. Logic-L input to this pin powers-up two LDOs in this order: LDO1 first, and then LDO2. Logic-L
also powers-down LDO2 first, and then LDO1.
SEQ 8 Logic-H to this pin powers-up two LDOs in this order: LDO2 first, and then LDO1. Logic-H also powers-down LDO1
first, and then LDO2.
SEQ should be hard-wired to either IN or GND depending on the sequencing mode required.
LDO1 soft-start setting. Leave this pin open for the default ramp up setting or connect a capacitor, 10 nF or less,
SS1 12 between this pin and GND to program V
OUT1
ramp-up slew rate. Do not connect a regular oscilloscope probe for
monitoring.
LDO2 soft-start setting. Leave this pin open for the default ramp up setting or connect a capacitor between this pin
SS2 4
and GND to program V
OUT2
ramp-up slew rate. Do not connect a regular oscilloscope probe for monitoring.
TEST 11 Test pin for test and debugging purposes only. Do not connect this pin.
Output of SVS3. This is an open-drain output terminal and a pull-up resistor is required. The typical connection is
VDET 5
100 kΩ to IN. When V
MON
> V
SVS3
, VDET outputs logic-H; when V
MON
< V
SVS3
, VDET is logic-L.
Monitor input voltage of third voltage detector. A resistor divider on this pin between the voltage rail to be monitored
VMON 16
and GND sets the threshold voltage. The detect threshold is 1.206 V.
LDO1 output voltage setting. Logic-H input sets V
OUT1
to 1.9 V. Logic-L sets V
OUT1
to 1.8 V. It is recommended to tie
VSET 9
this pin either to IN or GND depending on voltage required for the application.
Pad for thermal dissipation. Tie this pin to GND with vias through the board to internal heat spreading layers as well
Thermal pad
as the back side of the PCB.
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Product Folder Link(s): TPS75005