Datasheet

TPS75005
www.ti.com SBVS144C –NOVEMBER 2011–REVISED APRIL 2012
Normal Power-Up and Power-Down Sequence
Figure 32 shows oscilloscope waveforms of the TPS75005 in a normal power-up and power-down sequence with
SEQ = L. Refer to the time lines labeled Event A through Event H.
1. Before Event A, the TPS75005 is idle, waiting for an enable event.
(Power-Up Sequence Begins)
2. At Event A, EN goes to logic-H and the device immediately discharges a soft-start capacitor (C
SS1
) by
using a one-shot circuit. Then, the LDO1 soft-start circuit starts charging C
SS1
. The OUT1 voltage follows
the SS1 voltage. Time between Event A and Event B is defined as t
SS1
and can be programmed by C
SS1
.
3. At Event B, the OUT1 voltage exceeds the V
SVS1
threshold and the SVS1 delay circuit starts charging
C
CT1
. Time between Event B and Event C is defined as t
d(SVS1)
and can be programmed by C
CT1
.
4. At Event C, the CT1 voltage exceeds the V
CT1
threshold to discharge a soft-start capacitor (C
SS2
) using a
one-shot circuit. Then, the LDO2 soft-start circuit starts charging C
SS2
. The OUT2 voltage follows the
SS2 voltage. Time between Event C and Event D is defined as t
SS2
and can be programmed by C
SS2
.
5. At Event D, the OUT2 voltage exceeds the V
SVS2
threshold and the SVS2 delay circuit starts charging
C
CT2
. Time between Event D and Event E is defined as t
d(SVS2)
and can be programmed by C
CT2
.
(Power-Up Sequence Ends)
6. At Event E, the CT2 voltage exceeds the V
CT2
threshold and PG goes high to enable the C2000
controller. The TPS75005 is up and running as long as a disable or an error event occurs.
(Power-Down Sequence Begins)
7. At Event F, EN goes to logic-L and the device immediately turns PG to logic-L so that the C2000
controller is disabled. Then, an internal signal EN2 goes to logic-L in order to disable LDO2. Because the
active pull-down switch is enabled by SW2 (= EN2) signal, the OUT2 voltage starts decreasing (note that
this ramp-down speed depends on the application circuits).
8. At Event G, the OUT2 voltage underruns the V
DOWN2
threshold and an internal signal EN1 goes into
logic-L in order to disable LDO1. Because the active pull-down switch is enabled by SW1 (= EN1) signal,
the OUT1 voltage starts decreasing (note that this ramp-down speed is depends on the application
circuits).
9. At Event H, the OUT1 voltage underruns the V
DOWN1
threshold to return back to the idle state.
(Power-Down Sequence Ends)
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