Datasheet

TPS75005
SBVS144C –NOVEMBER 2011–REVISED APRIL 2012 www.ti.com
Internal Enable Signals and Pull-Down Switches
As shown in Figure 1, LDO1 is controlled by the internal signal EN1, and LDO2 is controlled by EN2. SW1 and
SW2 are the inverse signals of EN1 and EN2, respectively. Whenever LDO1 and LDO2 are disabled, that means
EN1 and EN2 are logic-L, respectively. The corresponding output node(s) is discharged by an internal MOSFET
and 360-Ω resistor controlled by SW1 and SW2.
These pull-down switches ensure that every power-down sequence is completed in a reasonable, finite time.
See the Power-Down Monitoring section for a very important notice.
LDO1 Voltage Setting (VSET)
LDO1 can be configured as either a 1.8-V regulator or a 1.9-V regulator by the configuration of the VSET pin.
When VSET is connected to ground, LDO1 outputs 1.8 V; when VSET is connected to the level of logic-H, LDO1
outputs 1.9 V.
Current Limit
The TPS75005 internal current limit helps protect the regulator during unexpected fault conditions. During current
limit, the output sources a fixed 900mA. If kept in current limit for an extended period of time, the device will
thermally shutdown.
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