Datasheet

LDO1
LDO2
OUT1
OUT1-S
OUT2
OUT2-S
10 Fm
V
DDIO-n
V
DD-n
V
DDIO-3
V
DD-3
V
DDIO-2
V
DD-2
V
DDIO-1
V
DD-1
0.1 Fm
0.1 Fm
0.1 Fm0.1 Fm 0.1 Fm
0.1 Fm
0.1 Fm
0.1 Fm
C2000
Controller
10 Fm
TPS75005
SBVS144C NOVEMBER 2011REVISED APRIL 2012
www.ti.com
LDO BLOCKS
The TPS75005 integrates two high-bandwidth LDOs for powering the V
DD
and V
DDIO
pins of the C2000
controllers.
Input Capacitor
Although an input capacitor is not required for LDO stability, it is recommended to connect a 10-μF capacitor
across the input supply near the device. In addition to input capacitor consideration, pay attention to the printed
circuit board (PCB) design in order to reduce source impedance.
X5R- and X7R-type capacitors are highly recommended because they have minimal variation in value and ESR
over temperature. Maximum ESR should be less than 1.0 .
Output Capacitors
The TPS75005 is designed to be stable using standard ceramic capacitors with capacitance values 4.7 μF or
greater. In order to meet C2000 transient requirements, a 10-µF output capacitor at each of OUT1 and OUT2 is
recommended.
X5R- and X7R-type capacitors are highly recommended because they have minimal variation in value and ESR
over temperature. Maximum ESR should be less than 1.0 .
See the Sense Pins (OUT1_S AND OUT2_S) section for more details.
Sense Pins (OUT1_S AND OUT2_S)
The TPS75005 has output voltage sensing pins OUT1_S and OUT2_S. OUT1_S should be connected to OUT1
at the output capacitor of LDO1, and OUT2_S to OUT2 at the output capacitor of LDO2. Both output capacitors
should be placed close to the device to minimize OUT1_S and OUT2_S trace. Figure 27 shows capacitor
placement.
Figure 27. Output Capacitors Placement and Sense Pins
When the C2000 controller is placed far from the TPS75005 on a PCB, it is recommended to connect the output
capacitors of OUT1 and OUT2 as close as possible to the TPS75005 device in order to route OUT1 and OUT2
node to a C2000 controller, and to place 0.1-µF ceramic capacitors for each of the V
DD
and V
DDIO
pins.
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