Datasheet

2
3
4
5
6 7 8 9 10
1
11
14
13
12
15
21 20 19 18 1617
PWPD NC IN IN EN VMON
PGVSETSEQGNDGND
VDET
SS2
CT2
OUT2_S
OUT2
TEST
SS1
CT1
OUT1_S
OUT1
EN
R3
100 kW
VIN
C3
10 mF
V
DDIO
C8
10 mF
V
DD
R2
3.7 kW
R1
10 kW
EN
C2
10 mF
VIN
V
IN
Power Supply
R6
100 kW
PG
TPS75005
SBVS144C –NOVEMBER 2011–REVISED APRIL 2012 www.ti.com
APPLICATION INFORMATION
Design Guidelines
Figure 25 and Figure 26 show a basic schematic and PCB layout for applications using the internal default
settings for power-good delay and rise time of the LDO1 and LDO2 outputs at turn on. This configuration is
typical for applications involving the targeted C2000 microcontrollers. The unused adjustment pins, CT1, CT2,
SS1, and SS2, are left open or floating. Connecting the SEQ and VSET pins to ground selects the turn-on
sequence and the output voltage of LDO1. The open-drain outputs at PG and VDET are pulled up to the input
voltage through 100-kΩ resistors. VDET is connected to enable the TPS75005 when the input voltage exceeds
the SVS voltage set by resistor divider R1 and R2 to VMON. For highly dynamic loads, like that of the C2000
microcontroller, the input capacitor, C2, and the output capacitors, C3 and C8, are specified to be 10-µF, X5R or
X7R, 10-V, ceramic capacitors in order to meet transient performance requirements.
Figure 25. Configuration for F280x, F281x, F223x and F2833x Controllers
(Set to automatically sequence C2000 when V
IN
> 4.5 V)
(C2, C3, C8 / 10-µF X5R ceramic capacitors)
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Product Folder Link(s): TPS75005