Datasheet

1 ms/div
2 V/div
50 mV/div
VDET
V
EXT_SVS
= 2.385 V
V
EXT_SVS
= 2.398 V
Thermal Guidelines and Layout Recommendations www.ti.com
4.3 EXT SVS Voltage Monitor Behavior
Figure 5 shows the VDET output as the EXT SVS input drops below regulation voltage.
Figure 5. Third Voltage Monitor Behavior (VDET) when EXT SVS Drops Below Regulation
5 Thermal Guidelines and Layout Recommendations
Thermal management is a key component of design of any power converter and is especially important
when the power dissipation in the LDO is high. Use the following formula to approximate the maximum
power dissipation for a particular ambient temperature:
T
J
= T
A
+ P
D
× θ
JA
Where T
J
is the junction temperature, T
A
is the ambient temperature, P
D
is the power dissipation in the
device (in watts), and θ
JA
is the thermal resistance from junction to ambient. All temperatures are in
degrees Celsius (°C). The absolute maximum silicon junction temperature, T
J
, must not be allowed to
exceed +150°C. The steady-state maximum of T
J
must not exceed +125°C. +125°C is the highest
allowable junction temperature at which the TPS75005 can operate for an extended period of time. The
layout design must use copper trace and plane areas carefully as thermal sinks (in order to prevent T
J
from exceeding the absolute maximum rating under all temperature conditions and voltage conditions
across the part).
The designer should carefully consider the thermal design of the PCB for optimal performance over
temperature. This EVM employs two copper plane layers as primary spreading layers to sink and spread
conducted heat from the TPS75005. Internal layer 1 (shown in Figure 8) is primarily used as a signal/trace
layer, but it also contains enough 1-oz copper area to assist with heat dissipation. Internal layer 2 (shown
in Figure 9) is an unbroken ground plane (2.3 in by 1.7 in) and thermal spreading layer made of 1-oz
copper. The bottom layer (shown in Figure 10) is also a thermal spreading layer, but consists of 2-oz
copper.
Table 1 shows the thermal parameters measured in the laboratory for this particular layout. This
measurement is made for illustrative purposes only, and should not be used to replace the more
conservative JEDEC-based thermal characteristics found in the TPS75005 product data sheet. The
JEDEC model only uses two 1-oz internal spreading planes (3 in by 3 in). Keep in mind that thermal
parameters can vary significantly if there is not sufficient copper to act as a heat sink for the part.
Table 1. Approximate Thermal Resistance, θ
JA
, and Maximum Power Dissipation
Max Dissipation Max Dissipation
without Derating without Derating
Board Package θ
JA
(T
A
= +25°C) (T
A
= +70°C)
TPS75005EVM-023 RGW 18°C/W 6.944 W 4.444 W
In addition, refer to the Texas Instruments thermal modeling tool, the PCB Thermal Calculator (available at
www.ti.com) to calculate the maximum junction temperature for a selectable internal copper spreading
area.
6
TPS75005EVM-023 SBVU019A–October 2011–Revised October 2011
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