Datasheet

200 s/divm

5 V/div

2 V/div

VOUT1

VOUT2

5 ms/div

5 V/div

2 V/div

VOUT1

VOUT2

OUT

VOUT2

50 s/divm

200 mA/div

20 mV/div

3.37 V Offset

OUT

VOUT1

20 s/divm

200 mA/div

20 mV/div

1.85 V Offset

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Test Results

4 Test Results

This section provides typical performance waveforms for the TPS75005EVM-023 PCB. These tests were

performed with VIN = 5 V.

4.1 Start-Up and Shutdown Sequence

Figure 1 and Figure 2 show the start-up and shutdown sequence, respectively, when JP3 is not installed.

If JP3 is installed, then VOUT1 and VOUT2 swap the order in which they turn on and off. For these tests,

VIN = 5.0 V, with no load. The start-up ramps of VOUT1 and VOUT2 can be adjusted by modifying C6

and C5, respectively.

Figure 1. Start-Up Sequence, SEQ Set to Logic Low Figure 2. Shutdown Sequence, SEQ Set to Logic Low

4.2 Output Load Transient

Figure 3 and Figure 4 show the load transient responses of LDO-1 and LDO-2, respectively, for a load

step from 10 mA to 500 mA. VIN is set at 5.0 V. Figure 3 shows the load transient response at VOUT1 of

LDO-1 when VOUT1 is set to 1.8 V. Figure 4 shows the load transient response at VOUT2 of LDO-2.

Figure 3. Load Step and Transient Response of Figure 4. Load Step and Transient Response of LDO-2

LDO-1, VSET Set to Logic Low

SBVU019A–October 2011–Revised October 2011 TPS75005EVM-023

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