Datasheet

3.0A
Current
Limit
0.7A
Time
R1 = 33mΩ
R1 = 143mΩ
C
SS1
= 0.022µF
C
SS1
= 0.022µF
C
SS1
= 0.01µF
C
SS1
= 0.01µF
V
OUT
+ V
FB
ǒ
R
5
R
6
)1
Ǔ
TPS75003
SBVS052I –OCTOBER 2004–REVISED AUGUST 2010 www.ti.com
Figure 25. Effects of C
SS1
and R
1
on Current Ramp Limit
This soft-start current limit ramp can be used to provide inrush current control or output voltage ramp control.
While the current limit ramp can be easily understood by looking at Figure 25, the output voltage ramp is a
complex function of many variables. The dominant variables in this process are V
OUT1
, C
SS1
, I
OUT1
, and R
1
. Less
important variables are V
IN1
and L
1
.
The best way to set a target start-up time is through bench measurement under target conditions, adjusting C
SS1
to get the desired startup profile. To stay above a minimum start-up time, set the nominal start-up time to
approximately five times the minimum. To stay below a maximum time, set the nominal start-up time at one-fifth
of the maximum. Fastest start-up times occur at maximum V
IN1
, with minimum V
OUT1
, L
1
, C
OUT1
, C
SS1
, and I
OUT1
.
Slowest start-up times occur under opposite conditions.
Refer to Figure 10 to Figure 14 for characterization curves showing how the start-up profile is affected by these
critical parameters.
Output Voltage Setting Selection (Buck Controllers)
Output voltage is set using two resistors as shown for Buck2 in Figure 1. Output voltage is then calculated using
Equation 13:
(13)
where V
FB
= 1.22V.
LDO OPERATION
The TPS75003 LDO uses a PMOS pass element and is offered in an adjustable version for ease of
programming to any output voltage. When used to power V
CC,AUX
it is set to 2.5V; it can optionally be set to other
output voltages to power other circuitry. The LDO has integrated soft-start, independent enable, and short-circuit
and thermal protection. The LDO can be used to power V
CC,AUX
on the Xilinx Spartan-3 FPGA when 3.3V JTAG
signals are used as described in Application Note SLVA159 (available for download from www.ti.com).
Input Capacitor Selection (LDO)
Although an input capacitor is not required, it is good analog design practice to connect a 0.1mF to 10mF low ESR
capacitor across the input supply near the regulator. This capacitor counteracts reactive input sources and
improves transient response, stability, and ripple rejection. A higher value capacitor may be needed if large, fast
rise-time load transients are anticipated, or if the device is located far from its power source.
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