Datasheet

0.1µF
R
D
Q L
f = measured resonant
frequency at switch node
R = 2πfL
TPS75003
www.ti.com SBVS052I –OCTOBER 2004–REVISED AUGUST 2010
Table 4. Capacitors Tested with the TPS75003
PART NUMBER MANUFACTURER CAPACITANCE ESR VOLTAGE RATING
6TPB47M (PosCap) Sanyo 47mF 0.1Ω 6.3V
T491D476M010AS Kemet 47mF 0.8Ω 10V
B45197A Epco 47mF 0.175Ω 16V
B45294−R1107−M40 Epco 100mF 0.045Ω 6.3V
594D476X0016C2 Vishay 47mF 0.11Ω 16V
594D127X96R3C2 Vishay 120mF 0.085Ω 6.3V
TPSC107K006R0150 AVX 100mF 0.15Ω 6.3V
6TPS100MC Sanyo 100mF 0.45Ω 6.3V
OPERATION (BUCK CONTROLLERS)
Channels 1 and 2 contain two identical non-synchronous buck controllers that use minimum on-time/minimum
off-time hysteretic control. (Refer to Figure 1.) For clarity, BUCK1 is used throughout the discussion of device
operation. When V
OUT1
is below its target, an external PMOS (Q1) is turned on for at least the minimum on-time,
increasing current through the inductor (L1) until V
OUT1
reaches its target value or the current limit (set by R1) is
reached. Once either of these conditions is met, the PMOS is switched off for at least the minimum off-time of
the device. After the minimum off-time has passed, the output voltage is monitored and the switch is turned on
again when necessary.
When output current is low, the buck controllers operate in discontinuous mode. In this mode, each switching
cycle begins at zero inductor current, rises to a maximum value, then falls back to zero current. When current
reaches zero on the falling edge, ringing occurs at the resonant frequency of the inductor and stray switch node
capacitance. This operation is normal; it does not affect circuit performance, and can be minimized if desired by
using an RC snubber and/or a resistor in series with the gate of the PMOS, as shown in Figure 22.
Figure 22. RC Snubber and Series Gate Resistor Used to Minimize Ringing
At higher output currents, the TPS75003 operates in continuous mode. In continuous mode, there is no ringing at
the switch node and V
OUT
is equal to V
IN
times the duty cycle of the switching waveform.
When V
IN
approaches or falls below V
OUT
, the buck controllers operate in 100% duty cycle mode, fully turning on
the external PMOS to allow regulation at lower dropout than would otherwise be possible.
Enable (Buck Controllers)
The enable pins (EN1 and EN2) for the buck controllers are active high. When the enable pin is driven low and
input voltage is present at IN1 or IN2, an on-chip FET is turned on to discharge the soft-start pin SS1 or SS2,
respectively. If the soft-start feature is being used, enable should be driven high at least 10ms after V
IN
is applied
to ensure this discharge cycle occurs.
UVLO (Buck Controllers)
An under-voltage lockout circuit is present to prevent turning on the external PMOS (Q1 or Q2) until a reliable
operating voltage is reached on the appropriate regulator (IN1 or IN2). This prevents the buck controllers from
mis-operation at low input voltages.
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