Datasheet

V (
N RMS
mV )=25xV (V)
OUT
mV
RMS
V
TPS74901
GND
SS
OUT
FB
EN
IN
BIAS
V
IN
V
OUT
R
2
R
1
C
SS
C
IN
C
V
BIAS
C
BIAS
R
C
OUT
TPS749xx
www.ti.com SBVS082G –JUNE 2007–REVISED NOVEMBER 2010
The maximum recommended soft-start capacitor is OUTPUT NOISE
0.015mF. Larger soft-start capacitors can be used and
The TPS749xx provides low output noise when a
will not damage the device; however, the soft-start
soft-start capacitor is used. When the device reaches
capacitor discharge circuit may not be able to fully
the end of the soft-start cycle, the soft-start capacitor
discharge the soft-start capacitor when enabled.
serves as a filter for the internal reference. By using a
Soft-start capacitors larger than 0.015mF could be a
0.001mF soft-start capacitor, the output noise is
problem in applications where the user needs to
reduced by half and is typically 30mV
RMS
for a 1.2V
rapidly pulse the enable pin and still requires the
output (10Hz to 100kHz). Further increasing C
SS
has
device to soft-start from ground. C
SS
must be
little effect on noise, Because most of the output
low-leakage; X7R, X5R, or C0G dielectric materials
noise is generated by the internal reference, the
are preferred. Refer to Table 2 for suggested
noise is a function of the set output voltage. The RMS
soft-start capacitor values.
noise with a 0.001mF soft-start capacitor is given in
Equation 3.
SEQUENCING REQUIREMENTS
V
IN
, V
BIAS
, and V
EN
can be sequenced in any order
(3)
without causing damage to the device. However, for
the soft-start function to work as intended, certain
The low output noise of the TPS749xx makes it a
sequencing rules must be applied. Connecting EN to
good choice for powering transceivers, PLLs, or other
IN is acceptable for most applications as long as V
IN
noise-sensitive circuitry.
is greater than 1.1V and the ramp rate of V
IN
and
V
BIAS
is faster than the set soft-start ramp rate. If the
ENABLE/SHUTDOWN
ramp rate of the input sources is slower than the set
The enable (EN) pin is active high and is compatible
soft-start time, the output tracks the slower supply
with standard digital signaling levels. V
EN
below 0.4V
minus the dropout voltage until it reaches the set
turns the regulator off, while V
EN
above 1.1V turns the
output voltage. If EN is connected to BIAS, the device
regulator on. Unlike many regulators, the enable
will soft-start as programmed, provided that V
IN
is
circuitry has hysteresis and deglitching for use with
present before V
BIAS
. If V
BIAS
and V
EN
are present
relatively slowly ramping analog signals. This
before V
IN
is applied and the set soft-start time has
configuration allows the TPS749xx to be enabled by
expired, then V
OUT
tracks V
IN
. If the soft-start time has
connecting the output of another supply to the EN
not expired, the output tracks V
IN
until V
OUT
reaches
pin. The enable circuitry typically has 50mV of
the value set by the charging soft-start capacitor.
hysteresis and a deglitch circuit to help avoid on-off
Figure 28 shows the use of an RC-delay circuit to
cycling because of small glitches in the V
EN
signal.
hold off V
EN
until V
BIAS
has ramped. This technique
can also be used to drive EN from V
IN
. An external
The enable threshold is typically 0.8V and varies with
control signal can also be used to enable the device
temperature and process variations. Temperature
after V
IN
and V
BIAS
are present.
variation is approximately –1mV/°C; process variation
accounts for most of the rest of the variation to the
NOTE: When V
BIAS
and V
EN
are present and V
IN
is
0.4V and 1.1V limits. If precise turn-on timing is
not supplied, this device outputs approximately 50mA
required, a fast rise-time signal must be used to
of current from OUT. Although this condition will not
enable the TPS749xx.
cause any damage to the device, the output current
may charge up the OUT node if total resistance
If not used, EN can be connected to either IN or
between OUT and GND (including external feedback
BIAS. If EN is connected to IN, it should be
resistors) is greater than 10kΩ.
connected as close as possible to the largest
capacitance on the input to prevent voltage droops on
that line from triggering the enable circuit.
POWER-GOOD
The power-good (PG) pin is an open-drain output and
can be connected to any 5.5V or lower rail through an
external pull-up resistor. This pin requires at least
1.1V on V
BIAS
in order to have a valid output. The PG
output is high-impedance when V
OUT
is greater than
V
IT
+ V
HYS
. If V
OUT
drops below V
IT
or if V
BIAS
drops
Figure 28. Soft-Start Delay Using an RC Circuit
below 1.9V, the open-drain output turns on and pulls
on Enable
the PG output low. The PG pin also asserts when the
device is disabled. The recommended operating
Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback 13