Datasheet

1.1 Performance Specification Summary
1.2 Modifications
2 Input/Output Connector Descriptions
Input/Output Connector Descriptions www.ti.com
Table 1 provides a summary of the TPS74901EVM-210 performance specifications. All specifications are
given for an ambient temperature of 25 ° C.
Table 1. Typical Performance Specification Summary
VOLTAGE RANGE CURRENT RANGE
(V) (mA)
CONDITION
MIN TYP MAX MIN TYP MAX
V
BIAS
supply I
O
= 3 A and V
IN
= V
BIAS
2.99
(1)
5 5.5 2000
V
IN
supply I
O
= 3 A and V
BIAS
- V
O
> 3.25 V 1.52
(1)
5.5
(2)
3000
V
OUT
1.16
(3)
1.20 1.24
(3)
3000
(2)
(1)
This is the minimum voltage to provide the maximum output current in the table assuming the typical V
BIAS
voltage is applied.
Lower output currents are achievable with lower V
IN
and V
BIAS
voltages. See the data sheet for V
IN
to V
OUT
and V
BIAS
to V
OUT
dropout data.
(2)
Linear regulator power dissipation is computed as P
D
= (V
IN
– V
OUT
) × I
OUT
. As specified in the data sheet, the regulator's
package has a finite power dissipation rating depending on the ambient temperature, board type, and airflow. Using V
IN
and/or
V
OUT
voltages other than the typical voltages recommended in the table or using the EVM in an environment with an ambient
temperature higher than 25 ° C significantly reduces the maximum allowed output current. See the data sheet for the regulator
package's thermal resistance data, and see the application report Digital Designer's Guide to Linear Voltage Regulators and
Thermal Management (SLVA118 ) for a full explanation.
(3)
The EVM uses ± 1% feedback resistors. Therefore, the EVM output tolerance is the ± 2% internal reference tolerance plus
2 × (1 – V
REF
/V
OUT
) × TOL
FBRES
= 2 × (1– 0.8V/1.2V) × ± 2% = 1.3% or ± 3.3%. For tighter output tolerance, tighter tolerance
feedback resistors must be used.
To aid user customization of the EVM, the board was designed with devices having 0603 or larger
footprints. A real implementation likely occupies less total board space.
Changing components can improve or degrade EVM performance. For example, adding a larger output
capacitor reduces output voltage undershoot but lengthens response time after a load transient event.
J1–VIN/GND This terminal block has both a positive and ground return connection to the power input (V
IN
)
supply. The leads to the input supply should be twisted and kept as short as possible.
J2–GND This header is the return connection for the bias (V
BIAS
) supply.
J3–VIN This header is a positive connection to the power input supply (V
IN
). Its use is recommended for
low power (i.e., I
IN
= I
OUT
< 1 A) evaluation or as a voltage test point.
J4–VBIAS This header is the positive connection for the bias (V
BIAS
) supply.
J5–GND This header is a ground return connection to the power input (V
IN
) supply. Its use is
recommended for low power (i.e., I
IN
= I
OUT
< 1A) evaluation or as a ground test point.
J6–VOUT This header is the positive connection for the output load on V
OUT
. Its use is recommended for
low power (i.e., I
IN
= I
OUT
< 1 A) evaluation only or as a voltage test point.
J7–GND This header is the ground return connection for the output load. Its use is recommended for low
power (i.e., I
IN
= I
OUT
< 1 A) evaluation or as a ground test point.
J8–VOUT/GND This terminal block has both a positive and ground return connection for the output load.
The leads to the output load should be twisted and kept as short as possible.
JP1– EN When this jumper is installed, the enable pin (EN) is tied to VIN, thereby enabling the device.
When this jumper is removed, EN is pulled to ground by resistor R4, thereby disabling the device.
S1 - This switch connects to the EN pin of the IC and allows the user to turn the IC ON or OFF by
connecting enable to either V
BIAS
or ground through a pulldown resistor.
TP1 – This is a Kelvin test point to V
IN
.
2 TPS74901EVM-210 SLVU190B – April 2007 – Revised July 2008
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