Datasheet

R =
θJA
(150°C - T )
A
P
D
P =(V V ) I- ´
D IN OUT OUT
TPS74801-Q1
www.ti.com SLVSAI4B –OCTOBER 2010–REVISED JULY 2013
The internal current limit protection circuitry of the TPS74801-Q1 is designed to protect against overload
conditions. It is not intended to allow operation above the rated current of the device. Continuously running the
TPS74801-Q1 above the rated current degrades device reliability.
THERMAL PROTECTION
Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is enabled.
Depending on power dissipation, thermal resistance, and ambient temperature the thermal protection circuit may
cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of
overheating.
Activation of the thermal protection circuit indicates excessive power dissipation or inadequate heatsinking. For
reliable operation, junction temperature should be limited to 150°C maximum. To estimate the margin of safety in
a complete design (including heatsink), increase the ambient temperature until thermal protection is triggered;
use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least 40°C
above the maximum expected ambient condition of the application. This condition produces a worst-case junction
temperature of 150°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS74801-Q1 is designed to protect against overload conditions. It is not
intended to replace proper heatsinking. Continuously running the TPS74801-Q1 into thermal shutdown degrades
device reliability.
LAYOUT RECOMMENDATIONS AND POWER DISSIPATION
An optimal layout can greatly improve transient performance, PSRR, and noise. To minimize the voltage drop on
the input of the device during load transients, the capacitance on IN and BIAS should be connected as close as
possible to the device. This capacitance also minimizes the effects of parasitic inductance and resistance of the
input source and can, therefore, improve stability. To achieve optimal transient performance and accuracy, the
top side of R
1
in Figure 25 should be connected as close as possible to the load. If BIAS is connected to IN, it is
recommended to connect BIAS as close to the sense point of the input supply as possible. This connection
minimizes the voltage drop on BIAS during transient conditions and can improve the turn-on response.
Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the thermal pad
is critical to avoiding thermal shutdown and ensuring reliable operation. Power dissipation of the device depends
on input voltage and load conditions and can be calculated using Equation 4:
(4)
Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input
voltage necessary to achieve the required output voltage regulation.
The primary conduction path for heat is through the exposed pad to the printed circuit board (PCB). The pad can
be connected to ground or be left floating; however, it should be attached to an appropriate amount of copper
PCB area to ensure the device does not overheat. The maximum junction-to-ambient thermal resistance
depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of
the device and can be calculated using Equation 5:
(5)
Knowing the maximum R
θJA
, the minimum amount of PCB copper area needed for appropriate heatsinking can
be estimated using Figure 29.
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