Datasheet

Reference
SimplifiedBlock Diagram
V
OUT
OUT
BIAS
FB
IN
V
IN
V =3.3V 5%
BIAS
±
V =3.3V 5V
V =1.5V
I =1.5A
Efficiency=45%
IN
OUT
OUT
±
C
OUT
Reference
SimplifiedBlock Diagram
V
OUT
OUT
BIAS
FB
IN
V =5V 5%
BIAS
±
V =1.8V
V =1.5V
I =1.5A
Efficiency=83%
IN
OUT
OUT
C
OUT
TPS74801-Q1
SLVSAI4B –OCTOBER 2010–REVISED JULY 2013 www.ti.com
Characteristics section. Because the TPS74801-Q1 is stable with output capacitors as low as 2.2 μF, many
applications may then need very little capacitance at the LDO output. For these applications, local bypass
capacitance for the powered device may be sufficient to meet the transient requirements of the application. This
design reduces the total solution cost by avoiding the need to use expensive, high-value capacitors at the LDO
output.
DROPOUT VOLTAGE
The TPS74801-Q1 offers very low dropout performance, making it well-suited for high-current, low V
IN
/ low V
OUT
applications. The low dropout of the TPS74801-Q1 allows the device to be used in place of a DC-DC converter
and still achieve good efficiency. This provides designers with the power architecture for their application to
achieve the smallest, simplest, and lowest cost solution.
There are two different specifications for dropout voltage with the TPS74801-Q1. The first specification (shown in
Figure 26) is referred to as V
IN
Dropout and is used when an external bias voltage is applied to achieve low
dropout. This specification assumes that V
BIAS
is at least 3.25 V
(1)
above V
OUT
, which is the case for V
BIAS
when
powered by a 5-V rail with 5% tolerance and with V
OUT
= 1.5 V. If V
BIAS
is higher than V
OUT
3.25 V
(1)
, V
IN
dropout
is less than specified.
Figure 26. Typical Application of the TPS74801-Q1 Using an Auxiliary Bias Rail
Figure 27. Typical Application of the TPS74801-Q1 Without an Auxiliary Bias Rail
The second specification (shown in Figure 27) is referred to as V
BIAS
Dropout and applies to applications where
IN and BIAS are tied together. This option allows the device to be used in applications where an auxiliary bias
voltage is not available or low dropout is not required. Dropout is limited by BIAS in these applications because
V
BIAS
provides the gate drive to the pass FET; therefore, V
BIAS
must be 1.6 V above V
OUT
. Because of this usage,
IN and BIAS tied together easily consume huge power. Pay attention not to exceed the power rating of the IC
package.
(1) 3.25 V is a test condition of this device and can be adjusted by referring to Figure 8.
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