Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - LDO voltage regulator Positivbe, adjustable VSON 10 (3x3)

0.5V/div V

OUT

1V/div

Time(1ms/div)

=2.2nF

=1nF

=0nF

1.2V

TPS74801

GND

IN PG

BIAS

OUT

BIAS

OUT

TPS74801-Q1

www.ti.com

SLVSAI4B –OCTOBER 2010–REVISED JULY 2013

1.5 A Low-Dropout Linear Regulator with Programmable Soft-Start

Check for Samples: TPS74801-Q1

FEATURES

APPLICATIONS

• Qualified for Automotive Applications

• FPGA Applications

• AEC-Q100 Qualified with the Following • DSP Core and I/O Voltages

Results:

• Post-Regulation Applications

– Device Temperature Grade 1: –40°C to

• Applications with Special Start-Up Time or

125°C Ambient Operating Temperature

Sequencing Requirements

Range

• Hot-Swap and Inrush Controls

– Device HBM ESD Classification Level H2

– Device HBM ESD Classification Level C4B DESCRIPTION

The TPS74801-Q1 low-dropout (LDO) linear regulator

• V

OUT

Range: 0.8 V to 3.6 V

provides an easy-to-use robust power management

• Ultralow V

Range: 0.8 V to 5.5 V

solution for a wide variety of applications. User-

• V

BIAS

Range 2.7 V to 5.5 V

programmable soft-start minimizes stress on the input

power source by reducing capacitive inrush current

• Low Dropout: 60 mV typ at 1.5 A, V

BIAS

= 5 V

on start-up. The soft-start is monotonic and well-

• Power Good (PG) Output Allows Supply

suited for powering many different types of

Monitoring or Provides a Sequencing Signal

processors and ASICs. The enable input and power

for Other Supplies

good output allow easy sequencing with external

• 2% Accuracy Over Line/Load/Temperature

regulators. This complete flexibility permits the user to

configure a solution that meets the sequencing

• Programmable Soft-Start Provides Linear

requirements of FPGAs, DSPs, and other

Voltage Startup

applications with special start-up requirements.

• V

BIAS

Permits Low V

Operation with Good

A precision reference and error amplifier deliver 2%

Transient Response

accuracy over load, line, temperature, and process.

• Stable with Any Output Capacitor ≥ 2.2 μF

The device is stable with any type of capacitor

• Available in a Small 3-mm x 3-mm x 1-mm

greater than or equal to 2.2 μF, and is fully specified

SON-10 and 5 x 5 QFN-20 Packages

from –40°C to 105°C for the DRC package, and from

–40°C to 125°C for the RGW package. The

TPS74801-Q1 is offered in a small 3-mm × 3-mm

SON-10 package, yielding a highly compact, total

solution size. It is also available in a 5 x 5 QFN-20 for

compatibility with the TPS74401.

Figure 1. Typical Application Circuit (Adjustable) Figure 2. Turn-On Response

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (29 pages)

PAGE 1
TPS74801-Q1 www.ti.com SLVSAI4B – OCTOBER 2010 – REVISED JULY 2013 1.5 A Low-Dropout Linear Regulator with Programmable Soft-Start Check for Samples: TPS74801-Q1 FEATURES APPLICATIONS • • • • • • 1 2 • • • • • • • • • • Qualified for Automotive Applications AEC-Q100 Qualified with the Following Results: – Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range – Device HBM ESD Classification Level H2 – Device HBM ESD Classification Level C4B VOUT Range: 0.8 V to 3.
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TPS74801-Q1 SLVSAI4B – OCTOBER 2010 – REVISED JULY 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS74801-Q1 www.ti.com SLVSAI4B – OCTOBER 2010 – REVISED JULY 2013 THERMAL INFORMATION TPS74801-Q1 (2) THERMAL METRIC (1) Junction-to-ambient thermal resistance (3) θJA (4) RGW DRC 20 PINS 10 PINS 35.6 41.5 θJCtop Junction-to-case (top) thermal resistance 33.3 78 θJB Junction-to-board thermal resistance (5) 15 N/A ψJT Junction-to-top characterization parameter (6) 0.4 0.7 ψJB Junction-to-board characterization parameter (7) 15.2 11.
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TPS74801-Q1 SLVSAI4B – OCTOBER 2010 – REVISED JULY 2013 www.ti.com ELECTRICAL CHARACTERISTICS At VEN = 1.1 V, VIN = VOUT + 0.3 V, CBIAS = 0.1 μF, CIN = COUT = 10 μF, CNR = 1 nF, IOUT = 50 mA, VBIAS = 5 V, TA = –40°C to 105°C (DRC) and TA = –40°C to 125°C (RGW), unless otherwise noted. Typical values are at TA = 25°C. TPS74801-Q1 PARAMETER TEST CONDITIONS VIN Input voltage range VBIAS Bias pin voltage range VREF Internal reference (Adj.) VOUT MIN MAX UNIT VOUT + VDO 5.5 V 2.7 5.5 V 0.
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TPS74801-Q1 www.ti.com SLVSAI4B – OCTOBER 2010 – REVISED JULY 2013 BLOCK DIAGRAM IN Current Limit BIAS UVLO OUT Thermal Limit 0.44mA VOUT R1 SS CSS Soft-Start Discharge 0.8V Reference FB PG EN Hysteresis and Deglitch R2 0.9 ´ VREF GND Table 1. Standard 1% Resistor Values for Programming the Output Voltage (1) (1) R1 (kΩ) R2 (kΩ) VOUT (V) Short Open 0.8 0.619 4.99 0.9 1.13 4.53 1 1.37 4.42 1.05 1.87 4.99 1.1 2.49 4.99 1.2 4.12 4.75 1.5 3.57 2.87 1.8 3.57 1.
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TPS74801-Q1 SLVSAI4B – OCTOBER 2010 – REVISED JULY 2013 www.ti.com NC NC NC OUT 4 3 2 1 IN 6 20 OUT IN 7 19 OUT IN 8 18 OUT PG 9 17 NC BIAS 10 16 FB 13 14 15 NC SS TPS74801 GND NC EN 5 8 FB 7 SS 6 GND 12 BIAS 4 GND Thermal Pad 11 PG 3 IN 10 OUT 9 OUT IN 2 EN IN 1 RGW PACKAGE 5 x 5 QFN (TOP VIEW) 5 DRC PACKAGE 3-mm x 3-mm SON (TOP VIEW) PIN DESCRIPTIONS 6 NAME DRC (SON) RGW (QFN) IN 1, 2 5-8 DESCRIPTION Input to the device. EN 5 11 Enable pin.
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TPS74801-Q1 www.ti.com SLVSAI4B – OCTOBER 2010 – REVISED JULY 2013 TYPICAL CHARACTERISTICS At TA = 25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 μF, CBIAS = 4.7 μF, and COUT = 10 μF, unless otherwise noted. VIN LINE REGULATION 0.20 0.4 0.15 0.3 0.10 Change in VOUT (%) Change in VOUT (%) VBIAS LINE REGULATION 0.5 -40°C 0.05 0 +25°C -0.05 +125°C -0.01 0.2 -40°C 0.1 0 -0.1 +125°C -0.2 +25°C -0.3 -0.15 -0.4 -0.20 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.
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TPS74801-Q1 SLVSAI4B – OCTOBER 2010 – REVISED JULY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = 25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 μF, CBIAS = 4.7 μF, and COUT = 10 μF, unless otherwise noted. VIN DROPOUT VOLTAGE vs (VBIAS – VOUT) AND TEMPERATURE (TA) 200 2000 160 VDO (VBIAS - VOUT) (mV) VDO (VIN - VOUT) (mV) 2200 IOUT = 0.
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TPS74801-Q1 www.ti.com SLVSAI4B – OCTOBER 2010 – REVISED JULY 2013 TYPICAL CHARACTERISTICS (continued) At TA = 25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 μF, CBIAS = 4.7 μF, and COUT = 10 μF, unless otherwise noted. BIAS PIN CURRENT vs IOUT AND TEMPERATURE (TA) 2.0 1.8 2.0 1.8 +125°C 1.6 +125°C 1.6 1.4 1.4 IBIAS (mA) IBIAS (mA) BIAS PIN CURRENT vs VBIAS AND TEMPERATURE (TA) 1.2 1.0 0.8 +25°C -40°C 0.6 1.2 +25°C 1.0 0.8 0.6 0.4 0.4 0.2 0.
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TPS74801-Q1 SLVSAI4B – OCTOBER 2010 – REVISED JULY 2013 www.ti.com TYPICAL CHARACTERISTICS At TA = 25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 5 V, IOUT = 1 A, VEN = VIN = 1.8 V, VOUT = 1.5 V, CIN = 1 μF, CBIAS = 4.7 μF, and COUT = 10 μF, unless otherwise noted. VBIAS LINE TRANSIENT VIN LINE TRANSIENT CSS = 1nF COUT = 10mF (Ceramic) COUT = 10mF (Ceramic) 100mV/div 100mV/div COUT = 2.2mF (Ceramic) 100mV/div CSS = 1nF 3.8V 5.0V 1V/div 1V/div 1V/ms 3.3V 1V/ms 1.
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TPS74801-Q1 www.ti.com SLVSAI4B – OCTOBER 2010 – REVISED JULY 2013 APPLICATION INFORMATION The TPS74801-Q1 belongs to a family of low dropout regulators that feature soft-start capability. These regulators use a low current bias input to power all internal control circuitry, allowing the NMOS pass transistor to regulate very low input and output voltages. The use of an NMOS-pass FET offers several critical advantages for many applications.
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TPS74801-Q1 SLVSAI4B – OCTOBER 2010 – REVISED JULY 2013 www.ti.com Characteristics section. Because the TPS74801-Q1 is stable with output capacitors as low as 2.2 μF, many applications may then need very little capacitance at the LDO output. For these applications, local bypass capacitance for the powered device may be sufficient to meet the transient requirements of the application. This design reduces the total solution cost by avoiding the need to use expensive, high-value capacitors at the LDO output.
PAGE 13
TPS74801-Q1 www.ti.com SLVSAI4B – OCTOBER 2010 – REVISED JULY 2013 PROGRAMMABLE SOFT-START The TPS74801-Q1 features a programmable, monotonic, voltage-controlled soft-start that is set with an external capacitor (CSS). This feature is important for many applications because it eliminates power-up initialization problems when powering FPGAs, DSPs, or other processors.
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TPS74801-Q1 SLVSAI4B – OCTOBER 2010 – REVISED JULY 2013 www.ti.com VIN VOUT OUT IN R1 CIN BIAS TPS74801 COUT FB R2 R VBIAS EN CBIAS C GND SS CSS Figure 28. Soft-Start Delay Using an RC Circuit to Enable the Device OUTPUT NOISE The TPS74801-Q1 provides low output noise when a soft-start capacitor is used. When the device reaches the end of the soft-start cycle, the soft-start capacitor serves as a filter for the internal reference. By using a 0.
PAGE 15
TPS74801-Q1 www.ti.com SLVSAI4B – OCTOBER 2010 – REVISED JULY 2013 The internal current limit protection circuitry of the TPS74801-Q1 is designed to protect against overload conditions. It is not intended to allow operation above the rated current of the device. Continuously running the TPS74801-Q1 above the rated current degrades device reliability. THERMAL PROTECTION Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the device to cool.
PAGE 16
TPS74801-Q1 SLVSAI4B – OCTOBER 2010 – REVISED JULY 2013 www.ti.com 140 120 qJA (°C/W) 100 80 60 40 20 0 0 Note: 1 2 4 5 7 3 6 Board Copper Area (in2) 8 9 10 θJA value at board size of 9 in2 (that is, 3-in × 3-in) is a JEDEC standard. Figure 29. θJA vs Board Size Figure 29 shows the variation of θJA as a function of ground plane copper area in the board.
PAGE 17
TPS74801-Q1 www.ti.com SLVSAI4B – OCTOBER 2010 – REVISED JULY 2013 12 YJT and YJB (°C/W) 10 YJB 8 DRC RGW 6 4 2 YJT 0 0 1 2 3 4 5 6 7 8 9 10 Board Copper Area (in2) Figure 30. ΨJT and ΨJB vs Board Size For a more detailed discussion of why TI does not recommend using θJC(top) to determine thermal characteristics, refer to application report SBVA025, Using New Thermal Metrics, available for download at www.ti.com.
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TPS74801-Q1 SLVSAI4B – OCTOBER 2010 – REVISED JULY 2013 www.ti.com REVISION HISTORY Changes from Revision A (February 2011) to Revision B Page • Added AEC-Q100 info to Features. ...................................................................................................................................... 1 • Added an extra sentence to the Description. ........................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 19-Aug-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS74801QRGWRQ1 VQFN RGW 20 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TPS74801TDRCRQ1 SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 19-Aug-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS74801QRGWRQ1 VQFN RGW 20 3000 367.0 367.0 35.0 TPS74801TDRCRQ1 SON DRC 10 3000 367.0 367.0 35.
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