Datasheet

P =(V V ) I- ´
D IN OUT OUT
R =
qJA
(+125 C T )° -
A
P
D
140
120
100
80
60
40
20
0
q
JA
( C/W)
°
0 1 2 3
4 5
6
7
8 9 10
Board Copper Area ( )in
2
DRC
RGW
TPS74801
SBVS074J –JANUARY 2007– REVISED JANUARY 2012 www.ti.com
INTERNAL CURRENT LIMIT R
1
in Figure 25 should be connected as close as
possible to the load. If BIAS is connected to IN, it is
The TPS74801 features a factory-trimmed, accurate
recommended to connect BIAS as close to the sense
current limit that is flat over temperature and supply
point of the input supply as possible. This connection
voltage. The current limit allows the device to supply
minimizes the voltage drop on BIAS during transient
surges of up to 2A and maintain regulation. The
conditions and can improve the turn-on response.
current limit responds in approximately 10μs to
reduce the current during a short-circuit fault. Knowing the device power dissipation and proper
sizing of the thermal plane that is connected to the
The internal current limit protection circuitry of the
thermal pad is critical to avoiding thermal shutdown
TPS74801 is designed to protect against overload
and ensuring reliable operation. Power dissipation of
conditions. It is not intended to allow operation above
the device depends on input voltage and load
the rated current of the device. Continuously running
conditions and can be calculated using Equation 4:
the TPS74801 above the rated current degrades
device reliability. (4)
Power dissipation can be minimized and greater
THERMAL PROTECTION
efficiency can be achieved by using the lowest
possible input voltage necessary to achieve the
Thermal protection disables the output when the
required output voltage regulation.
junction temperature rises to approximately +160°C,
allowing the device to cool. When the junction
On both the SON (DRC) and QFN (RGW) packages,
temperature cools to approximately +140°C, the
the primary conduction path for heat is through the
output circuitry is enabled. Depending on power
exposed pad to the printed circuit board (PCB). The
dissipation, thermal resistance, and ambient
pad can be connected to ground or be left floating;
temperature the thermal protection circuit may cycle
however, it should be attached to an appropriate
on and off. This cycling limits the dissipation of the
amount of copper PCB area to ensure the device
regulator, protecting it from damage as a result of
does not overheat. The maximum junction-to-ambient
overheating.
thermal resistance depends on the maximum ambient
temperature, maximum device junction temperature,
Activation of the thermal protection circuit indicates
and power dissipation of the device and can be
excessive power dissipation or inadequate
calculated using Equation 5:
heatsinking. For reliable operation, junction
temperature should be limited to +125°C maximum.
To estimate the margin of safety in a complete design
(5)
(including heatsink), increase the ambient
temperature until thermal protection is triggered; use
Knowing the maximum R
θJA
, the minimum amount of
worst-case loads and signal conditions. For good
PCB copper area needed for appropriate heatsinking
reliability, thermal protection should trigger at least
can be estimated using Figure 29.
+40°C above the maximum expected ambient
condition of the application. This condition produces a
worst-case junction temperature of +125°C at the
highest expected ambient temperature and
worst-case load.
The internal protection circuitry of the TPS74801 is
designed to protect against overload conditions. It is
not intended to replace proper heatsinking.
Continuously running the TPS74801 into thermal
shutdown degrades device reliability.
LAYOUT RECOMMENDATIONS AND POWER
DISSIPATION
An optimal layout can greatly improve transient
performance, PSRR, and noise. To minimize the
voltage drop on the input of the device during load
Note: θ
JA
value at board size of 9in
2
(that is, 3in ×
transients, the capacitance on IN and BIAS should be
3in) is a JEDEC standard.
connected as close as possible to the device. This
Figure 29. θ
JA
vs Board Size
capacitance also minimizes the effects of parasitic
inductance and resistance of the input source and
can, therefore, improve stability. To achieve optimal
transient performance and accuracy, the top side of
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