Datasheet

V
OUT
C
OUT
10 Fm
TPS74701
GND
EN
FB
IN PG
BIAS
SS
OUT
V
IN
R
1
R
2
R
3
C
IN
1 Fm
C
SS
V
BIAS
C
BIAS
1 Fm
V =0.8
OUT
´ 1+
R
1
R
2
)(
TPS74701
www.ti.com SBVS099F –NOVEMBER 2007–REVISED NOVEMBER 2010
APPLICATION INFORMATION
The TPS74701 belongs to a family of low-dropout
R
1
and R
2
can be calculated for any output voltage
regulators that feature soft-start capability. These
using the formula shown in Figure 24. Refer to
regulators use a low current bias input to power all
Table 1 for sample resistor values of common output
internal control circuitry, allowing the NMOS pass
voltages. In order to achieve the maximum accuracy
transistor to regulate very low input and output
specifications, R
2
should be less than or equal to
voltages.
4.99kΩ.
The use of an NMOS-pass FET offers several critical
INPUT, OUTPUT, AND BIAS CAPACITOR
advantages for many applications. Unlike a PMOS
REQUIREMENTS
topology device, the output capacitor has little effect
on loop stability. This architecture allows the
The device is designed to be stable for all available
TPS74701 to be stable with any capacitor type of
types and values of output capacitors greater than or
value 2.2mF or greater. Transient response is also
equal to 2.2mF. The device is also stable with multiple
superior to PMOS topologies, particularly for low V
IN
capacitors in parallel, which can be of any type or
applications.
value.
The TPS74701 features a programmable
The capacitance required on the IN and BIAS pins
voltage-controlled soft-start circuit that provides a
strongly depends on the input supply source
smooth, monotonic start-up and limits startup inrush
impedance. To counteract any inductance in the
currents that may be caused by large capacitive
input, the minimum recommended capacitor for V
IN
loads. A power good (PG) output is available to allow
and V
BIAS
is 1mF. If V
IN
and V
BIAS
are connected to
supply monitoring and sequencing of other supplies.
the same supply, the recommended minimum
An enable (EN) pin with hysteresis and deglitch
capacitor for V
BIAS
is 4.7mF. Good quality, low ESR
allows slow-ramping signals to be used for
capacitors should be used on the input; ceramic X5R
sequencing the device. The low V
IN
and V
OUT
and X7R capacitors are preferred. These capacitors
capability allows for inexpensive, easy-to-design, and
should be placed as close the pins as possible for
efficient linear regulation between the multiple supply
optimum performance.
voltages often present in processor-intensive
systems.
TRANSIENT RESPONSE
Figure 24 illustrates the typical application circuit for
The TPS74701 was designed to have excellent
the TPS74701 adjustable output device.
transient response for most applications with a small
amount of output capacitance. In some cases, the
transient response may be limited by the transient
response of the input supply. This limitation is
especially true in applications where the difference
between the input and output is less than 300mV. In
this case, adding additional input capacitance
improves the transient response much more than just
adding additional output capacitance would do. With
a solid input supply, adding additional output
capacitance reduces undershoot and overshoot
during a transient event; refer to Figure 21 in the
Typical Characteristics section. Because the
TPS74701 is stable with output capacitors as low as
Figure 24. Typical Application Circuit for the
2.2mF, many applications may then need very little
TPS74701 (Adjustable)
capacitance at the LDO output. For these
applications, local bypass capacitance for the
powered device may be sufficient to meet the
transient requirements of the application. This design
reduces the total solution cost by avoiding the need
to use expensive, high-value capacitors at the LDO
output.
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