Datasheet
IN
IN
IN
PG
BIAS
OUT
OUT
OUT
NC
FB/SNS
TPS744xx
IN
EN
11
GND
12
NC
13
NC
14
SS
15
6
7
8
9
10
20
19
18
17
16
5
NC4
NC3
NC2
OUT1
GND
OUT
GND
BIAS
IN
FB/
SNS
SS
1 2 3 4
5
6
EN
7
TPS744xx
www.ti.com
SBVS066O –DECEMBER 2005–REVISED MARCH 2013
PIN CONFIGURATIONS
RGW PACKAGE
KTW PACKAGE
5 × 5 QFN-20
DDPAK-7
(TOP VIEW)
SURFACE-MOUNT
PIN DESCRIPTIONS
NAME KTW (DDPAK) RGW (QFN) DESCRIPTION
IN 5 5–8 Unregulated input to the device.
Enable pin. Driving this pin high enables the regulator. Driving this pin low puts
EN 7 11
the regulator into shutdown mode. This pin must not be left floating.
SS 1 15 Soft-Start pin. A capacitor connected on this pin to ground sets the start-up
time. If this pin is left floating, the regulator output soft-start ramp time is
typically 100μs.
BIAS 6 10 Bias input voltage for error amplifier, reference, and internal control circuits.
Power-Good (PG) is an open-drain, active-high output that indicates the status
of V
OUT
. When V
OUT
exceeds the PG trip threshold, the PG pin goes into a
high-impedance state. When V
OUT
is below this threshold the pin is driven to a
PG N/A 9 low-impedance state. A pull-up resistor from 10kΩ to 1MΩ should be connected
from this pin to a supply up to 5.5V. The supply can be higher than the input
voltage. Alternatively, the PG pin can be left floating if output monitoring is not
necessary.
This pin is the feedback connection to the center tap of an external resistor
FB divider network that sets the output voltage. This pin must not be left floating.
(Adjustable version only.)
2 16
This pin is the sense connection to the load device. This pin must be connected
SNS
to V
OUT
and must not be left floating. (Fixed versions only.)
OUT 3 1, 18–20 Regulated output voltage. No capacitor is required on this pin for stability.
No connection. This pin can be left floating or connected to GND to allow better
NC N/A 2–4, 13, 14, 17
thermal contact to the top-side plane.
GND 4 12 Ground
PAD/TAB Should be soldered to the ground plane for increased thermal performance.
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