Datasheet

120
100
80
60
40
20
0
q
JA
( C/W)
°
0 1 2 3
4 5
6
7
8 9 10
BoardCopperArea(in )
2
q
JA
(KTW)
q
JA
(RGW)
R
qJA
+
ǒ
)125°C * T
A
Ǔ
P
D
P
D
+
ǒ
V
IN
* V
OUT
Ǔ
I
OUT
TPS744xx
www.ti.com SBVS066O –DECEMBER 2005–REVISED MARCH 2013
THERMAL PROTECTION Power dissipation of the device depends on input
voltage and load conditions, and can be calculated
Thermal protection disables the output when the
using Equation 4:
junction temperature rises to approximately +155°C,
allowing the device to cool. When the junction
(4)
temperature cools to approximately +140°C, the
Power dissipation can be minimized and greater
output circuitry is enabled. Depending on power
efficiency can be achieved by using the lowest
dissipation, thermal resistance, and ambient
possible input voltage necessary to achieve the
temperature the thermal protection circuit may cycle
required output voltage regulation.
on and off. This cycling limits the dissipation of the
regulator, protecting it from damage as a result of
On the QFN (RGW) package, the primary conduction
overheating.
path for heat is through the exposed pad to the
printed circuit board (PCB). The pad can be
Activation of the thermal protection circuit indicates
connected to ground or be left floating; however, it
excessive power dissipation or inadequate
should be attached to an appropriate amount of
heatsinking. For reliable operation, junction
copper PCB area to ensure the device will not
temperature should be limited to +125°C maximum.
overheat. On the DDPAK (KTW) package, the
To estimate the margin of safety in a complete design
primary conduction path for heat is through the tab to
(including heatsink), increase the ambient
the PCB. That tab should be connected to ground.
temperature until thermal protection is triggered; use
The maximum junction-to-ambient thermal resistance
worst-case loads and signal conditions. For good
depends on the maximum ambient temperature,
reliability, thermal protection should trigger at least
maximum device junction temperature, and power
+30°C above the maximum expected ambient
dissipation of the device and can be calculated using
condition of the application. This condition produces a
Equation 5:
worst-case junction temperature of +125°C at the
highest expected ambient temperature and worst-
case load.
(5)
The internal protection circuitry of the TPS744xx is
Knowing the maximum R
θJA
, the minimum amount of
designed to protect against overload conditions. It is
PCB copper area needed for appropriate heatsinking
not intended to replace proper heatsinking.
can be estimated using Figure 35.
Continuously running the TPS744xx into thermal
shutdown degrades device reliability.
LAYOUT RECOMMENDATIONS AND POWER
DISSIPATION
An optimal layout can greatly improve transient
performance, PSRR, and noise. To minimize the
voltage droop on the input of the device during load
transients, the capacitance on IN and BIAS should be
connected as close as possible to the device. This
capacitance also minimizes the effects of parasitic
inductance and resistance of the input source and
can therefore improve stability. To achieve optimal
transient performance and accuracy, the top side of
R
1
in Figure 30 should be connected as close as
possible to the load. If BIAS is connected to IN, it is
recommended to connect BIAS as close to the sense
Note: θ
JA
value at board size of 9in
2
(that is, 3in ×
point of the input supply as possible. This connection
3in) is a JEDEC standard.
minimizes the voltage droop on BIAS during transient
Figure 35. θ
JA
vs Board Size
conditions and can improve the turn-on response.
Knowing the device power dissipation and proper
Figure 35 shows the variation of θ
JA
as a function of
sizing of the thermal plane that is connected to the
ground plane copper area in the board. It is intended
tab or pad is critical to avoiding thermal shutdown
only as a guideline to demonstrate the effects of heat
and ensuring reliable operation.
spreading in the ground plane and should not be
white space
used to estimate actual thermal performance in real
application environments.
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