Datasheet

Reference
SimplifiedBlock Diagram
BIAS
FB
IN
V
IN
V =3.3V 5%
BIAS
±
V =3.3V 5%
V =1.5V
I =1.5A
Efficiency=45%
IN
OUT
OUT
±
V
OUT
OUT
Reference
SimplifiedBlock Diagram
V
OUT
OUT
BIAS
FB
IN
V =5V 5%
BIAS
±
V =1.8V
V =1.5V
I =1.5A
Efficiency=83%
IN
OUT
OUT
TPS744xx
SBVS066O –DECEMBER 2005–REVISED MARCH 2013 www.ti.com
TRANSIENT RESPONSE
The TPS744xx was designed to have transient
response within 5% for most applications without any
output capacitor. In some cases, the transient
response may be limited by the transient response of
the input supply. This limitation is especially true in
applications where the difference between the input
and output is less than 300mV. In this case, adding
additional input capacitance improves the transient
response much more than just adding additional
output capacitance. With a solid input supply, adding
additional output capacitance reduces undershoot
and overshoot during a transient at the expense of a
slightly longer V
OUT
recovery time. Refer to Figure 24
in the Typical Characteristics section. Because the
Figure 32. Typical Application of the TPS744xx
TPS744xx is stable without an output capacitor, many Using an Auxiliary Bias Rail
applications may allow for little or no capacitance at
the LDO output. For these applications, local bypass
The second specification (shown in Figure 33) is
capacitance for the device under power may be
referred to as V
BIAS
Dropout and is for users that wish
sufficient to meet the transient requirements of the
to tie IN and BIAS together. This option allows the
application. This design reduces the total solution
device to be used in applications where an auxiliary
cost by avoiding the need to use expensive high-
bias voltage is not available or low dropout is not
value capacitors at the LDO output.
required. Dropout is limited by BIAS in these
applications because V
BIAS
provides the gate drive to
DROPOUT VOLTAGE
the pass FET and therefore must be 1.62V above
V
OUT
. Because of this usage, IN and BIAS tied
The TPS744xx offers industry-leading dropout
together easily consume huge power. Pay attention
performance, making it well-suited for high-current
not to exceed the power rating of the IC package.
low V
IN
/low V
OUT
applications. The extremely low
dropout of the TPS744xx allows the device to be
used in place of a dc/dc converter and still achieve
good efficiencies. This efficiency allows users to
rethink the power architecture for their applications to
achieve the smallest, simplest, and lowest cost
solution.
There are two different specifications for dropout
voltage with the TPS744xx. The first specification
(illustrated in Figure 32) is referred to as V
IN
Dropout
and is for users that wish to apply an external bias
voltage to achieve low dropout. This specification
assumes that V
BIAS
is at least 1.62V above V
OUT
,
which is the case for V
BIAS
when powered by a 3.3V
rail with 5% tolerance and with V
OUT
= 1.5V. If V
BIAS
is higher than 3.3V × 0.95 or V
OUT
is less than 1.5V,
V
IN
dropout is less than specified.
Figure 33. Typical Application of the TPS744xx
Without an Auxiliary Bias
14 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated