Datasheet

P
D
+
ǒ
V
IN
* V
OUT
Ǔ
I
OUT
R
qJA
+
ǒ
)125°C * T
A
Ǔ
P
D
TPS74401-EP
www.ti.com SBVS122B –MARCH 2010–REVISED SEPTEMBER 2010
pull-up resistor for PG should be in the range of 10 The internal protection circuitry of the TPS74401 is
kΩ to 1 MΩ. The pull-up resistor for PG should be in designed to protect against overload conditions. It is
the range of 10 kΩ to 1 MΩ. PG is only provided on not intended to replace proper heatsinking.
the QFN package. If output voltage monitoring is not Continuously running the TPS74401 into thermal
needed, the PG pin can be left floating. shutdown degrades device reliability.
INTERNAL CURRENT LIMIT LAYOUT RECOMMENDATIONS AND POWER
DISSIPATION
The TPS74401 features a factory-trimmed, accurate
current limit that is flat over temperature and supply An optimal layout can greatly improve transient
voltage. The current limit allows the device to supply performance, PSRR, and noise. To minimize the
surges of up to 3.5 A and maintain regulation. The voltage droop on the input of the device during load
current limit responds in about 10 ms to reduce the transients, the capacitance on IN and BIAS should be
current during a short-circuit fault. Recovery from a connected as close as possible to the device. This
short-circuit condition is well-controlled and results in capacitance also minimizes the effects of parasitic
very little output overshoot when the load is removed. inductance and resistance of the input source and
See Figure 27 in the Typical Characteristics section can therefore improve stability. To achieve optimal
for short-circuit recovery performance. transient performance and accuracy, the top side of
R
1
in Figure 28 should be connected as close as
The internal current limit protection circuitry of the
possible to the load. If BIAS is connected to IN, it is
TPS74401 is designed to protect against overload
recommended to connect BIAS as close to the sense
conditions. It is not intended to allow operation above
point of the input supply as possible. This connection
the rated current of the device. Continuously running
minimizes the voltage droop on BIAS during transient
the TPS74401 above the rated current degrades
conditions and can improve the turn-on response.
device reliability.
Knowing the device power dissipation and proper
sizing of the thermal plane that is connected to the
THERMAL PROTECTION
tab or pad is critical to avoiding thermal shutdown
Thermal protection disables the output when the
and ensuring reliable operation. Power dissipation of
junction temperature rises to approximately +155°C,
the device depends on input voltage and load
allowing the device to cool. When the junction
conditions, and can be calculated using Equation 4:
temperature cools to approximately +140°C, the
output circuitry is enabled. Depending on power (4)
dissipation, thermal resistance, and ambient
Power dissipation can be minimized and greater
temperature the thermal protection circuit may cycle
efficiency can be achieved by using the lowest
on and off. This cycling limits the dissipation of the
possible input voltage necessary to achieve the
regulator, protecting it from damage as a result of
required output voltage regulation.
overheating.
The primary conduction path for heat is through the
Activation of the thermal protection circuit indicates
exposed pad or tab to the printed circuit board (PCB).
excessive power dissipation or inadequate
The pad or tab can be connected to ground or be left
heatsinking. For reliable operation, junction
floating; however, it should be attached to an
temperature should be limited to +125°C maximum.
appropriate amount of copper PCB area to ensure
To estimate the margin of safety in a complete design
the device does not overheat. The maximum
(including heatsink), increase the ambient
junction-to-ambient thermal resistance depends on
temperature until thermal protection is triggered; use
the maximum ambient temperature, maximum device
worst-case loads and signal conditions. For good
junction temperature, and power dissipation of the
reliability, thermal protection should trigger at least
device, and can be calculated using Equation 5:
+30°C above the maximum expected ambient
condition of the application. This condition produces a
worst-case junction temperature of +125°C at the
(5)
highest expected ambient temperature and
worst-case load. Knowing the maximum R
qJA
and system air flow, the
minimum amount of PCB copper area needed for
appropriate heatsinking can be calculated using
Figure 32 through Figure 34.
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