Datasheet

V
N
ǒ
mV
RMS
Ǔ
+ 16
ǒ
mV
RMS
V
Ǔ
V
OUT
(
V
)
TPS74401
GND
SS
OUT
FB
EN
IN
BIAS
V
IN
V
OUT
R
2
R
1
C
SS
C
IN
1 Fm
C
V
BIAS
C
BIAS
1 Fm
R
TPS74401-EP
SBVS122B –MARCH 2010–REVISED SEPTEMBER 2010 www.ti.com
The maximum recommended soft-start capacitor is OUTPUT NOISE
0.015 mF. Larger soft-start capacitors can be used
The TPS74401 provides low output noise when a
and will not damage the device; however, the
soft-start capacitor is used. When the device reaches
soft-start capacitor discharge circuit may not be able
the end of the soft-start cycle, the soft-start capacitor
to fully discharge the soft-start capacitor when
serves as a filter for the internal reference. By using a
re-enabled. Soft-start capacitors larger than 0.015 mF
0.001-mF soft-start capacitor, the output noise is
could be a problem in applications where the user
reduced by half and is typically 19 mV
RMS
for a 1.2-V
needs to rapidly pulse the enable pin and still
output (100 Hz to 100 kHz). Because most of the
requires the device to soft-start from ground. C
SS
output noise is generated by the internal reference,
must be low-leakage; X7R, X5R, or C0G dielectric
the noise is a function of the set output voltage. The
materials are preferred. Refer to Table 3 for
RMS noise with a 0.001-mF soft-start capacitor is
suggested soft-start capacitor values.
given in Equation 3.
SEQUENCING REQUIREMENTS
The device can have V
IN
, V
BIAS
, and V
EN
sequenced (3)
in any order without causing damage to the device.
The low output noise of the TPS74401 makes it a
However, for the soft-start function to work as
good choice for powering transceivers, PLLs, or other
intended, certain sequencing rules must be applied.
noise-sensitive circuitry.
Enabling the device after V
IN
and V
BIAS
are present is
preferred, and can be accomplished using a digital
ENABLE/SHUTDOWN
output from a processor or supply supervisor. An
analog signal from an external RC circuit, as shown
The enable (EN) pin is active high and is compatible
in Figure 31, can also be used as long as the delay
with standard digital signaling levels. V
EN
below 0.4 V
time is long enough for V
IN
and V
BIAS
to be present.
turns the regulator off, while V
EN
above 1.1 V turns
the regulator on. Unlike many regulators, the enable
circuitry has hysteresis and deglitching for use with
relatively slow-ramping analog signals. This
configuration allows the TPS74401 to be enabled by
connecting the output of another supply to the EN
pin. The enable circuitry typically has 50 mV of
hysteresis and a deglitch circuit to help avoid on-off
cycling because of small glitches in the V
EN
signal.
The enable threshold is typically 0.8 V and varies with
temperature and process variations. Temperature
variation is approximately –1 mV/°C; therefore,
Figure 31. Soft-Start Delay Using an RC Circuit
process variation accounts for most of the variation in
on Enable
the enable threshold. If precise turn-on timing is
required, a fast rise-time signal should be used to
If a signal is not available to enable the device after
enable the TPS74401.
IN and BIAS, simply connecting EN to IN is
acceptable for most applications as long as V
IN
is
If not used, EN can be connected to either IN or
greater than 1.1 V and the ramp rate of V
IN
and V
BIAS
BIAS. If EN is connected to IN, it should be
is faster the set soft-start ramp rate. If the ramp rate
connected as close as possible to the largest
of the input sources is slower than the set soft-start
capacitance on the input to prevent voltage droops on
time, the output will track the slower supply minus the
that line from triggering the enable circuit.
dropout voltage until it reaches the set output voltage.
If EN is connected to BIAS, the device will soft-start
POWER-GOOD (QFN Package Only)
as programmed provided that V
IN
is present before
The power-good (PG) pin is an open-drain output and
V
BIAS
. If V
BIAS
and V
EN
are present before V
IN
is
can be connected to any 5.5 V or lower rail through
applied and the set soft-start time has expired then
an external pull-up resistor. This pin requires at least
V
OUT
will track V
IN
.
1.1 V on V
BIAS
in order to have a valid output. The PG
NOTE: When V
BIAS
and V
EN
are present and V
IN
is
output is high-impedance when V
OUT
is greater than
not supplied, this device outputs approximately 50 mA
V
IT
+ V
HYS
. If V
OUT
drops below V
IT
or if V
BIAS
drops
of current from OUT. Although this condition will not
below 1.9 V, the open-drain output turns on and pulls
cause any damage to the device, the output current
the PG output low. The PG pin also asserts when the
may charge up the OUT node if total resistance
device is disabled. The recommended operating
between OUT and GND (including external feedback
condition of PG pin sink current is up to 1 mA, so the
resistors) is greater than 10 kΩ.
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