Datasheet

TPS74401
GND
EN
FB
IN PG
SS
OUT
V
IN
V
OUT
V
PG
R
1
R
2
R
3
C
OUT
Optional
C
IN
1 Fm
C
SS
V
BIAS
C
BIAS
1 Fm
V =0.8
OUT
´ 1+
R
1
R
2
(
)
BIAS
TPS74401-EP
SBVS122B –MARCH 2010–REVISED SEPTEMBER 2010 www.ti.com
APPLICATION INFORMATION
The TPS74401 belongs to a family of new
generation ultra-low dropout regulators that feature
soft-start and tracking capabilities. These regulators
INPUT, OUTPUT, AND BIAS CAPACITOR
use a low current bias input to power all internal
REQUIREMENTS
control circuitry, allowing the NMOS pass transistor to
regulate very low input and output voltages.
The device does not require any output capacitor for
stability. If an output capacitor is needed, the device
The use of an NMOS-pass FET offers several critical
is designed to be stable for all available types and
advantages for many applications. Unlike a PMOS
values of output capacitance. The device is also
topology device, the output capacitor has little effect
stable with multiple capacitors in parallel, of any type
on loop stability. This architecture allows the
or value.
TPS74401 to be stable with any or even no output
capacitor. Transient response is also superior to
The capacitance required on the IN and BIAS pins
PMOS topologies, particularly for low V
IN
strongly depends on the input supply source
applications.
impedance. To counteract any inductance in the
input, the minimum recommended capacitor for V
IN
The TPS74401 features a programmable,
and V
BIAS
is 1 mF. If V
IN
and V
BIAS
are connected to
voltage-controlled soft-start circuit that provides a
the same supply, the recommended minimum
smooth, monotonic start-up and limits startup inrush
capacitor for V
BIAS
is 4.7 mF. Good quality, low ESR
currents that may be caused by large capacitive
capacitors should be used on the input; ceramic X5R
loads. A power-good (PG) output is available to allow
and X7R capacitors are preferred. These capacitors
supply monitoring and sequencing of other supplies.
should be placed as close the pins as possible for
An enable (EN) pin with hysteresis and deglitch
optimum performance.
allows slow-ramping signals to be used for
sequencing the device. The low V
IN
and V
OUT
capability allows for inexpensive, easy-to-design, and TRANSIENT RESPONSE
efficient linear regulation between the multiple supply
The TPS74401 was designed to have transient
voltages often present in processor intensive
response within 5% for most applications without any
systems.
output capacitor. In some cases, the transient
Figure 28 illustrates a typical application circuit for the response may be limited by the transient response of
TPS74401 adjustable output device. the input supply. This limitation is especially true in
applications where the difference between the input
R
1
and R
2
can be calculated for any output voltage
and output is less than 300 mV. In this case, adding
using the formula shown in Figure 28. Refer to
additional input capacitance improves the transient
Table 2 for sample resistor values of common output
response much more than just adding additional
voltages. In order to achieve the maximum accuracy
output capacitance. With a solid input supply, adding
specifications, R
2
should be ≤ 4.99 kΩ.
additional output capacitance reduces undershoot
and overshoot during a transient at the expense of a
slightly longer V
OUT
recovery time. Refer to Figure 22
in the Typical Characteristics section. Since the
TPS74401 is stable without an output capacitor,
many applications may allow for little or no
capacitance at the LDO output. For these
applications, local bypass capacitance for the device
under power may be sufficient to meet the transient
requirements of the application. This design reduces
the total solution cost by avoiding the need to use
expensive high-value capacitors at the LDO output.
Figure 28. Typical Application Circuit for the
TPS74401 (Adjustable)
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