Datasheet

R
qJA
+
(
)125
O
C * T
A
)
P
D
P
D
+
ǒ
V
IN
* V
OUT
Ǔ
I
OUT
120
100
80
60
40
20
0
q
JA
( C/W)
°
0 1 2 3
4 5
6
7
8 9 10
BoardCopperArea(in )
2
q
JA
(KTW)
q
JA
(RGW)
TPS743xx
SBVS065K –DECEMBER 2005–REVISED AUGUST 2010 www.ti.com
LAYOUT RECOMMENDATIONS AND POWER The maximum junction-to-ambient thermal resistance
DISSIPATION depends on the maximum ambient temperature,
maximum device junction temperature, and power
An optimal layout can greatly improve transient
dissipation of the device and can be calculated using
performance, PSRR, and noise. To minimize the
Equation 2:
voltage droop on the input of the device during load
transients, the capacitance on IN and BIAS should be
connected as close as possible to the device. This
(2)
capacitance also minimizes the effects of parasitic
white space
inductance and resistance of the input source and
can therefore improve stability. To achieve optimal
Knowing the maximum R
qJA
, the minimum amount of
transient performance and accuracy, the top side of
PCB copper area needed for appropriate heatsinking
R
1
in Figure 28 should be connected as close as
can be estimated using Figure 33.
possible to the load. If BIAS is connected to IN, it is
recommended to connect BIAS as close to the sense
point of the input supply as possible. This connection
minimizes the voltage droop on BIAS during transient
conditions and can improve the turn-on response.
Knowing the device power dissipation and proper
sizing of the thermal plane that is connected to the
tab or pad is critical to avoiding thermal shutdown
and ensuring reliable operation. Power dissipation of
the device depends on input voltage and load
conditions, and can be calculated using Equation 1:
(1)
Power dissipation can be minimized and greater
efficiency can be achieved by using the lowest
possible input voltage necessary to achieve the
required output voltage regulation.
Note: q
JA
value at board size of 9in
2
(that is, 3in ×
3in) is a JEDEC standard.
On the QFN (RGW) package, the primary conduction
Figure 33. q
JA
vs Board Size
path for heat is through the exposed pad to the
printed circuit board (PCB). The pad can be
connected to ground or be left floating; however, it
Figure 33 shows the variation of q
JA
as a function of
should be attached to an appropriate amount of
ground plane copper area in the board. It is intended
copper PCB area to ensure the device will not
only as a guideline to demonstrate the effects of heat
overheat. On the DDPAK (KTW) package, the
spreading in the ground plane and should not be
primary conduction path for heat is through the tab to
used to estimate actual thermal performance in real
the PCB. That tab should be connected to ground.
application environments.
NOTE: When the device is mounted on an
application PCB, it is strongly recommended to use
Ψ
JT
and Ψ
JB
, as explained in the Estimating Junction
Temperature section.
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