Datasheet

R
5
R
3
R
4
V
OUT
C
OUT
Optional
PG
OUT
SNS
IN
BIAS
TRACK
GND
V
IN
V
BIAS
C
IN
C
BIAS
V
TRACK
V
PG
TPS743xx
EN
R
1
R
5
R
3
R
4
R
2
V
OUT
C
OUT
Optional
PG
OUT
FB
IN
BIAS
TRACK
GND
V
IN
V
BIAS
C
IN
C
BIAS
V
TRACK
V
PG
TPS74301
V =0.8
OUT
´ 1+
R
1
R
2
(
)
EN
TPS743xx
SBVS065K –DECEMBER 2005–REVISED AUGUST 2010 www.ti.com
APPLICATION INFORMATION
The TPS743xx belongs to a family of new generation
R
1
and R
2
can be calculated for any output voltage
ultra-low dropout regulators that feature soft-start and
using the formula shown in Figure 28. Refer to
tracking capabilities. These regulators use a low
Table 1 for sample resistor values of common output
current bias input to power all internal control
voltages. In order to achieve the maximum accuracy
circuitry, allowing the NMOS pass transistor to
specifications, R
2
should be ≤ 4.99kΩ.
regulate very low input and output voltages.
FIXED VOLTAGE AND SENSE PIN
The use of an NMOS-pass FET offers several critical
advantages for many applications. Unlike a PMOS
Figure 29 illustrates a typical application circuit for the
topology device, the output capacitor has little effect
TPS743xx fixed output device.
on loop stability. This architecture allows the
TPS743xx to be stable with any or even no output
capacitor. Transient response is also superior to
PMOS topologies, particularly for low V
IN
applications.
The TPS743xx features a TRACK pin that allows the
output to track an external supply. This feature is
useful in minimizing the stress on ESD structures that
are present between the CORE and I/O power pins of
many processors. A power-good (PG) output is also
available to allow supply monitoring and sequencing
of follow-on supplies. To control the output turn-on,
Figure 29. Typical Application Circuit for the
an enable (EN) pin with hysteresis and deglitch is
TPS743xx (Fixed Voltage)
provided to allow slow-ramping signals to be utilized
for sequencing the device. The low V
IN
and V
OUT
capability allows for inexpensive, easy-to-design, and
A fixed voltage version of the TPS743xx has a sense
efficient linear regulation between the multiple supply
pin (SNS) so that the device can monitor its output
voltages often present in processor intensive
voltage at the load device pin(s) as closely as
systems.
possible. Unlike other TI fixed-voltage LDOs,
however, this pin must not be left floating; it must be
ADJUSTABLE VOLTAGE PART AND
connected to an output node. See the TI application
SETTING
report, Ultimate Regulation of with Fixed Output
Versions of the TPS742xx, TPS743xx, and TPS744xx
Figure 28 is a typical application circuit for the
(literature number SBVA024), available for download
TPS74301 adjustable device.
from the TI web site.
INPUT, OUTPUT, AND BIAS CAPACITOR
REQUIREMENTS
The device does not require any output capacitor for
stability. If an output capacitor is needed, the device
is designed to be stable for all available types and
values of output capacitance. The device is also
stable with multiple capacitors in parallel, of any type
or value.
The capacitance required on the IN and BIAS pins is
strongly dependent on the input supply source
impedance. To counteract any inductance in the
input, the minimum recommended capacitor for V
IN
and V
BIAS
is 1mF. If V
IN
and V
BIAS
are connected to
the same supply, the recommended minimum
capacitor for V
BIAS
is 4.7mF. Good quality, low ESR
Figure 28. Typical Application Circuit for the
capacitors should be used on the input; ceramic X5R
TPS74301 (Adjustable Version)
and X7R capacitors are preferred. These capacitors
should be placed as close the pins as possible for
optimum performance.
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