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TPS743xx

500mV/div

Time(20ms/div)

TRACK

I =500mA

OUT

Optional

OUT

BIAS

TRACK

GND

BIAS

TRACK

TPS74301

ADJUSTABLEVOLTAGEVERSION

OUT

Optional

OUT

SNS

BIAS

TRACK

GND

BIAS

TRACK

TPS743xx

FIXEDVOLTAGEVERSION

TPS743xx

www.ti.com

SBVS065K –DECEMBER 2005–REVISED AUGUST 2010

1.5A Ultra-LDO with Programmable Sequencing

Check for Samples: TPS743xx

FEATURES

DESCRIPTION

• Track Pin Allows for Flexible Power-Up

The TPS743xx low-dropout (LDO) linear regulators

Sequencing

provide an easy-to-use robust power management

• 1% Accuracy Over Line, Load, and

solution for a wide variety of applications. The

Temperature

TRACK pin allows the output to track an external

• Supports Input Voltages as Low as 0.9V with

supply. This feature is useful in minimizing the stress

External Bias Supply

on ESD structures that are present between the

CORE and I/O power pins of many processors. The

• Adjustable Output (0.8V to 3.6V)

enable input and power-good output allow easy

• Fixed Output (0.9V to 3.6V)

sequencing with external regulators. This complete

• Ultra-Low Dropout: 55mV at 1.5A (typ)

flexibility allows the user to configure a solution that

meets the sequencing requirements of FPGAs,

• Stable with Any or No Output Capacitor

DSPs, and other applications with special start-up

• Excellent Transient Response

requirements.

• Available in 5mm × 5mm × 1mm QFN and

A precision reference and error amplifier deliver 1%

DDPAK-7 Packages

accuracy over load, line, temperature, and process.

• Open-Drain Power-Good (5 × 5 QFN)

Each LDO is stable with low-cost ceramic output

• Active High Enable

capacitors and the family is fully specified from –40°C

to +125°C. The TPS743xx is offered in a small (5mm

× 5mm) QFN package, yielding a highly compact total

APPLICATIONS

solution size. For applications that require additional

• FPGA Applications

power dissipation, the DDPAK (KTW) package is also

• DSP Core and I/O Voltages

available.

• Post-Regulation Applications

• Applications with Special Start-Up Time or

Sequencing Requirements

Figure 1. Tracking Response

Figure 2. Typical Application Circuit

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

PAGE 1
TPS743xx TP S7 43x x TP S7 43 xx www.ti.com SBVS065K – DECEMBER 2005 – REVISED AUGUST 2010 1.5A Ultra-LDO with Programmable Sequencing Check for Samples: TPS743xx FEATURES 1 • 2 • • • • • • • • • • Track Pin Allows for Flexible Power-Up Sequencing 1% Accuracy Over Line, Load, and Temperature Supports Input Voltages as Low as 0.9V with External Bias Supply Adjustable Output (0.8V to 3.6V) Fixed Output (0.9V to 3.6V) Ultra-Low Dropout: 55mV at 1.
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TPS743xx SBVS065K – DECEMBER 2005 – REVISED AUGUST 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS743xx www.ti.com SBVS065K – DECEMBER 2005 – REVISED AUGUST 2010 THERMAL INFORMATION TPS743xx (2) THERMAL METRIC (1) RGW (20 PINS) KTW (7 PINS) qJA Junction-to-ambient thermal resistance (3) 30.5 20.1 qJCtop Junction-to-case (top) thermal resistance (4) 27.6 2.
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TPS743xx SBVS065K – DECEMBER 2005 – REVISED AUGUST 2010 www.ti.com ELECTRICAL CHARACTERISTICS At VEN = 1.1V, VIN = VOUT + 0.3V, CIN = CBIAS = 0.1mF, COUT = 10mF, IOUT = 50mA, VBIAS = 5.0V, and TJ = –40°C to +125°C, unless otherwise noted. Typical values are at TJ = +25°C. TPS743xx PARAMETER MAX UNIT VIN Input voltage range VOUT + VDO 5.5 V VBIAS Bias pin voltage range 2.375 5.25 V 0.804 V 3.6 V ±0.2 1 % VREF Internal reference (Adj.
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TPS743xx www.ti.com SBVS065K – DECEMBER 2005 – REVISED AUGUST 2010 BLOCK DIAGRAMS IN Current Limit BIAS UVLO VOUT Thermal Limit VTRACK < VREF = 1, VTRACK > VREF = 0 R1 1 TRACK 0 VOUT = 0.8 x (1 + 0.8V Reference R1 ) R2 FB PG Hysteresis and De-Glitch EN R2 0.9 ´ VREF GND Figure 3. Adjustable Voltage Version IN Current Limit BIAS UVLO OUT RSMALL SNS VTRACK < VREF = 1, VTRACK > VREF = 0 Thermal Limit 1 TRACK VOUT R1 0 0.8V Reference R2 PG EN Hysteresis and De-Glitch 0.
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TPS743xx SBVS065K – DECEMBER 2005 – REVISED AUGUST 2010 www.ti.com Table 1. Standard 1% Resistor Values for Programming the Output Voltage (1) (1) 6 R1 (kΩ) R2 (kΩ) VOUT (V) Short Open 0.8 0.619 4.99 0.9 1.13 4.53 1.0 1.37 4.42 1.05 1.87 4.99 1.1 2.49 4.99 1.2 4.12 4.75 1.5 3.57 2.87 1.8 3.57 1.69 2.5 3.57 1.15 3.3 VOUT = 0.
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TPS743xx www.ti.com SBVS065K – DECEMBER 2005 – REVISED AUGUST 2010 PIN CONFIGURATIONS IN NC NC NC OUT 5 4 3 2 1 RGW PACKAGE 5 × 5 QFN-20 (TOP VIEW) KTW PACKAGE DDPAK-7 SURFACE-MOUNT IN 6 20 OUT IN 7 19 OUT IN 8 18 OUT PG 9 17 NC BIAS 10 16 FB/SNS 11 12 13 14 15 EN GND NC NC SS TPS743xx GND 1 2 3 4 5 6 7 SS OUT IN EN FB/ GND BIAS SNS PIN DESCRIPTIONS NAME KTW (DDPAK) RGW (QFN) IN 5 5–8 Unregulated input to the device. EN 7 11 Enable pin.
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TPS743xx SBVS065K – DECEMBER 2005 – REVISED AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS At TJ = +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, EN = VIN, CIN = 1mF, CBIAS = 4.7mF, and COUT = 10mF, unless otherwise noted. LOAD REGULATION LOAD REGULATION 1.0 0.050 Referred to IOUT = 50mA 0.9 Referred to IOUT = 50mA 0.025 0.7 0.6 -40°C 0.5 0.4 +25°C 0.3 0 Change in VOUT (%) Change in VOUT (%) 0.8 0.2 +25°C -0.025 -0.050 -40°C -0.075 +125°C -0.100 0.
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TPS743xx www.ti.com SBVS065K – DECEMBER 2005 – REVISED AUGUST 2010 TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, EN = VIN, CIN = 1mF, CBIAS = 4.7mF, and COUT = 10mF, unless otherwise noted. VBIAS PSRR vs FREQUENCY 1400 90 1300 80 1200 +25°C +125°C 1100 Power-Supply Rejection (dB) Dropout Voltage (mV) VBIAS DROPOUT VOLTAGE vs IOUT AND TEMPERATURE 1000 -40°C 900 800 700 IOUT = 1.
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TPS743xx SBVS065K – DECEMBER 2005 – REVISED AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, EN = VIN, CIN = 1mF, CBIAS = 4.7mF, and COUT = 10mF, unless otherwise noted. IBIAS vs IOUT AND TEMPERATURE IBIAS vs VBIAS AND VOUT 2.85 3.0 2.8 2.65 +125°C 2.25 2.05 +25°C 1.85 1.65 +125°C 2.6 Bias Current (mA) Bias Current (mA) 2.45 -40°C 2.4 2.2 +25°C 2.0 1.8 1.6 -40°C 1.4 1.45 1.2 1.25 1.0 0 0.5 1.
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TPS743xx www.ti.com SBVS065K – DECEMBER 2005 – REVISED AUGUST 2010 TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, EN = VIN, CIN = 1mF, CBIAS = 4.7mF, and COUT = 10mF, unless otherwise noted. OUTPUT LOAD TRANSIENT RESPONSE TRACKING RESPONSE COUT = 2 x 470mF (OSCON) IOUT = 500mA 50mV/div COUT = 100mF (Cer.) 50mV/div VTRACK 50mV/div 500mV/div VPG COUT = 10mF (Cer.) COUT = 0mF 50mV/div VOUT 1.
PAGE 12
TPS743xx SBVS065K – DECEMBER 2005 – REVISED AUGUST 2010 www.ti.com APPLICATION INFORMATION The TPS743xx belongs to a family of new generation ultra-low dropout regulators that feature soft-start and tracking capabilities. These regulators use a low current bias input to power all internal control circuitry, allowing the NMOS pass transistor to regulate very low input and output voltages. R1 and R2 can be calculated for any output voltage using the formula shown in Figure 28.
PAGE 13
TPS743xx www.ti.com SBVS065K – DECEMBER 2005 – REVISED AUGUST 2010 TRANSIENT RESPONSE The TPS743xx was designed to have transient response within 5% for most applications without any output capacitor. In some cases, the transient response may be limited by the transient response of the input supply. This limitation is especially true in applications where the difference between the input and output is less than 300mV.
PAGE 14
TPS743xx SBVS065K – DECEMBER 2005 – REVISED AUGUST 2010 www.ti.com PROGRAMMABLE SEQUENCING WITH TRACK The TPS743xx features a track pin that allows the output to track an external supply at start-up. While the TRACK input is below 0.8V, the error amplifier regulates the FB pin to the TRACK input. Properly choosing the resistor divider network (R1 and R2) as shown in Figure 32 enables the regulator output to track the external supply to obtain a simultaneous or ratiometric start-up.
PAGE 15
TPS743xx www.ti.com ENABLE/SHUTDOWN The enable (EN) pin is active high and is compatible with standard digital signaling levels. VEN below 0.4V turns the regulator off, while VEN above 1.1V turns the regulator on. Unlike many regulators, the enable circuitry has hysteresis and deglitching for use with relatively slow-ramping analog signals. This configuration allows the TPS743xx to be enabled by connecting the output of another supply to the EN pin.
PAGE 16
TPS743xx SBVS065K – DECEMBER 2005 – REVISED AUGUST 2010 www.ti.com An optimal layout can greatly improve transient performance, PSRR, and noise. To minimize the voltage droop on the input of the device during load transients, the capacitance on IN and BIAS should be connected as close as possible to the device. This capacitance also minimizes the effects of parasitic inductance and resistance of the input source and can therefore improve stability.
PAGE 17
TPS743xx www.ti.com SBVS065K – DECEMBER 2005 – REVISED AUGUST 2010 ESTIMATING JUNCTION TEMPERATURE Using the thermal metrics ΨJT and ΨJB, shown in the Thermal Information table, the junction temperature can be estimated with corresponding formulas (given in Equation 3). For backwards compatibility, an older qJC,Top parameter is listed as well.
PAGE 18
TPS743xx SBVS065K – DECEMBER 2005 – REVISED AUGUST 2010 Looking at Figure 35, the RGW package thermal performance has negligible dependency on board size. The KTW package, however, does have a measurable dependency on board size. This dependency exists because the package shape is not point-symmetric to an IC center. In the KTW package, for example (see Figure 34), silicon is not beneath the measuring point of TT which is the center of the X and Y dimension, so that ΨJT has a dependency.
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TPS743xx www.ti.com SBVS065K – DECEMBER 2005 – REVISED AUGUST 2010 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision J (December, 2009) to Revision K Page • Replaced the Dissipation Ratings table with the Thermal Information table ........................................................................ 3 • Revised Layout Recommendations and Power Dissipation section ....................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS74301KTWR DDPAK/ TO-263 KTW 7 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TPS74301KTWT DDPAK/ TO-263 KTW 7 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TPS74301RGWR VQFN RGW 20 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS74301KTWR DDPAK/TO-263 KTW 7 500 367.0 367.0 45.0 TPS74301KTWT DDPAK/TO-263 KTW 7 50 367.0 367.0 45.0 TPS74301RGWR VQFN RGW 20 3000 367.0 367.0 35.0 TPS74301RGWT VQFN RGW 20 250 210.0 185.0 35.
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MECHANICAL DATA MPSF015 – AUGUST 2001 KTW (R-PSFM-G7) PLASTIC FLANGE-MOUNT 0.410 (10,41) 0.385 (9,78) 0.304 (7,72) –A– 0.006 –B– 0.303 (7,70) 0.297 (7,54) 0.0625 (1,587) H 0.055 (1,40) 0.0585 (1,485) 0.300 (7,62) 0.064 (1,63) 0.045 (1,14) 0.252 (6,40) 0.056 (1,42) 0.187 (4,75) 0.370 (9,40) 0.179 (4,55) 0.330 (8,38) H 0.296 (7,52) A 0.605 (15,37) 0.595 (15,11) 0.012 (0,305) C 0.000 (0,00) 0.019 (0,48) 0.104 (2,64) 0.096 (2,44) H 0.017 (0,43) 0.050 (1,27) C C F 0.034 (0,86) 0.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.