Datasheet

Reference
SimplifiedBlock Diagram
V
OUT
OUT
BIAS
FB
IN
V =5V 5%
BIAS
±
V =1.8V
V =1.5V
I =1.5A
Efficiency=83%
IN
OUT
OUT
Reference
SimplifiedBlock Diagram
V
OUT
OUT
BIAS
FB
IN
V
IN
V =3.3V 5%
BIAS
±
V =3.3V 5V
V =1.5V
I =1.5A
Efficiency=45%
IN
OUT
OUT
±
TPS742xx
www.ti.com
SBVS064L DECEMBER 2005REVISED NOVEMBER 2010
TRANSIENT RESPONSE
The TPS742xx was designed to have transient
response within 5% for most applications without any
output capacitor. In some cases, the transient
response may be limited by the transient response of
the input supply. This limitation is especially true in
applications where the difference between the input
and output is less than 300mV. In this case, adding
additional input capacitance improves the transient
response much more than just adding additional
output capacitance would do. With a solid input
supply, adding additional output capacitance reduces
undershoot and overshoot during a transient at the
expense of a slightly longer V
OUT
recovery time. Refer
Figure 30. Typical Application of the TPS742xx
to Figure 24 in the Typical Characteristics section.
Using an Auxiliary Bias Rail
Since the TPS742xx is stable without an output
capacitor, many applications may allow for little or no
capacitance at the LDO output. For these
The second specification (shown in Figure 31) is
applications, local bypass capacitance for the device
referred to as V
BIAS
Dropout and is for users who
under power may be sufficient to meet the transient
wish to tie IN and BIAS together. This option allows
requirements of the application. This design reduces
the device to be used in applications where an
the total solution cost by avoiding the need to use
auxiliary bias voltage is not available or low dropout is
expensive high-value capacitors at the LDO output.
not required. Dropout is limited by BIAS in these
applications because V
BIAS
provides the gate drive to
DROPOUT VOLTAGE
the pass FET and therefore must be 1.4V above
V
OUT
. Because of this usage, IN and BIAS tied
The TPS742xx offers industry-leading dropout
together easily consume huge power. Pay attention
performance, making it well-suited for high-current
not to exceed the power rating of the IC package.
low V
IN
/low V
OUT
applications. The extremely low
dropout of the TPS742xx allows the device to be
used in place of a DC/DC converter and still achieve
good efficiencies. This efficiency allows the user to
rethink the power architecture for their applications to
achieve the smallest, simplest, and lowest cost
solution.
There are two different specifications for dropout
voltage with the TPS742xx. The first specification
(illustrated in Figure 30) is referred to as V
IN
Dropout
and is for users who wish to apply an external bias
voltage to achieve low dropout. This specification
assumes that V
BIAS
is at least 1.62V above V
OUT
,
which is the case for V
BIAS
when powered by a 3.3V
rail with 5% tolerance and with V
OUT
= 1.5V. If V
BIAS
is higher than 3.3V × 0.95 or V
OUT
is less than 1.5V,
V
IN
dropout is less than specified.
Figure 31. Typical Application of the TPS742xx
Without an Auxiliary Bias
Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback 13