Datasheet

TPS740xx
www.ti.com SBVS091C –JUNE 2011– REVISED DECEMBER 2011
Table 2. Standard 1% Resistor Values for Programming the Output Voltage
R
1
(kΩ) R
2
(kΩ) V
OUT
(V)
Short Open 0.9
0.562 5.11 1.0
0.75 4.53 1.05
1.07 4.99 1.1
1.58 4.75 1.2
1.91 2.87 1.5
2.43 2.43 1.8
3.01 1.69 2.5
4.22 1.58 3.3
5.23 1.74 3.6
INPUT, OUTPUT, AND BIAS CAPACITOR REQUIREMENTS
The device is designed to be stable for all available types and values of output capacitors greater than or equal
to 2.2 μF. The device is also stable with multiple capacitors in parallel, which can be of any type or value.
The capacitance required on the IN and BIAS pins strongly depends on the input supply source impedance. To
counteract any inductance in the input, the minimum recommended capacitor for V
IN
and V
BIAS
is 1 μF. If V
IN
and
V
BIAS
are connected to the same supply, the recommended minimum capacitor for V
BIAS
is 4.7 μF. Good-quality,
low-ESR capacitors should be used on the input; ceramic X5R and X7R capacitors are preferred. These
capacitors should be placed as close to the pins as possible for optimum performance.
TRANSIENT RESPONSE
The TPS740xx is designed to have excellent transient response for most applications with a small amount of
output capacitance. In some cases, the transient response may be limited by the transient response of the input
supply. This limitation is especially true in applications where the difference between the input and output is less
than 300 mV. In these cases, adding additional input capacitance improves the transient response much more
than simply adding additional output capacitance. With a solid input supply, adding additional output capacitance
reduces undershoot and overshoot during a transient event; refer to the Typical Characteristics section. Because
the TPS740xx is stable with output capacitors as low as 2.2 μF, many applications may then need very little
capacitance at the LDO output. For these applications, local bypass capacitance for the powered device may be
sufficient to meet the transient requirements of the application. This design reduces the total solution cost by
avoiding the need to use expensive, high-value capacitors at the LDO output.
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