Datasheet

V
OUT
C
OUT
10 Fm
TPS74001
GND
FB
IN
BIAS
OUT
V
IN
R
1
R
2
C
IN
1 Fm
V
BIAS
C
BIAS
1 Fm
V =0.9
OUT
´
1+
R
1
R
2
)(
V
OUT
C
OUT
10 Fm
TPS740xx
GND
EN
IN
BIAS
OUT
V
IN
C
IN
1 Fm
V
BIAS
C
BIAS
1 Fm
TPS740xx
SBVS091C –JUNE 2011– REVISED DECEMBER 2011 www.ti.com
APPLICATION INFORMATION
The TPS740xx belongs to a family of low dropout (LDO) regulators. These regulators use a low-current bias
input to power all internal control circuitry, allowing the NMOS-pass transistor to regulate very low input and
output voltages.
The use of an NMOS-pass FET offers several critical advantages for many applications. Unlike a PMOS topology
device, the output capacitor has little effect on loop stability. This architecture allows the TPS740xx to be stable
with any capacitor type of 2.2 μF or greater. Transient response is also superior to PMOS topologies, particularly
for low V
IN
applications.
With the fixed output voltage version, an enable (EN) pin with hysteresis and deglitch allows slow-ramping
signals to be used for sequencing the device. The low V
IN
and V
OUT
capability is ideal for inexpensive,
easy-to-design, and efficient linear regulation between the multiple supply voltages often present in
processor-intensive systems.
Figure 31 illustrates the typical application circuit for the TPS74001 adjustable output device.
Figure 31. Typical Application Circuit for the TPS74001 (Adjustable)
R
1
and R
2
can be calculated for any output voltage using the formula shown in Figure 31. Table 2 lists sample
resistor values of common output voltages. In order to achieve the maximum accuracy specifications, R
2
is
recommended to be lower than 4.99 kΩ.
Figure 32 illustrates the typical application circuit for the TPS740xx fixed output device.
Figure 32. Typical Application Circuit for the TPS740xx (Fixed Voltage Versions)
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