Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - LDO voltage regulator Positive, fixed VSSOP 8

100

0.5 1.0

V (V V )(mV)-

DO IN OUT

I (A)

OUT

1.5

+125 C°

+25 C°

- °40 C

DropoutVoltage

TPS74001

GND

IN OUT

BIAS

OUT

BIAS

OUT

TypicalApplicationCircuit(Adjustable)

TPS740xx

www.ti.com

SBVS091C –JUNE 2011– REVISED DECEMBER 2011

1.5-A, Low-Voltage LDO Regulator with Dual Input Voltages

FEATURES

DESCRIPTION

The TPS740xx is a wide bandwidth, very low-dropout,

• Small Consumption Current: 3 mA Maximum

1.5-A voltage regulator ideal for powering

• Input Voltage Range:

microprocessors.

– V

: 1.2 V to 6.0 V

The TPS740xx uses a bias input supply to allow very

– V

BIAS

: 2.9 V to 6.0 V

low voltage of a main input supply. The main input

• Stable with Any Output Capacitance: ≥ 2.2 μF

supply operates from 1.2 V to 6.0 V and the bias

input supply requires between 3.0 V to 6.0 V for

• ±1% Initial Accuracy

proper operation. The TPS740xx offers adjustable

• Maximum Dropout Voltage (V

– V

OUT

output voltages down to 0.9 V.

300 mV Over Temperature

The TPS740xx requires a minimum of output

• Adjustable Output Voltage: Down to 0.9 V

capacitance. A small 2.2-μF ceramic capacitor is

• Ultra-Fast Transient Response

enough for its stability.

• Excellent Line and Load Regulation

The TPS740xx is available in an 8-pin power MSOP

• Logic-Controlled Shutdown Option

package and a 5-pin Jr S-PAK. Its operating

temparature range is –40°C to +125°C.

• Thermal Shutdown and Current Limit

Protection

• Power 8-Pin Mini Small-Outline Package

(MSOP) and Jr S-PAK™ packages.

• Junction Temperature Range: –40°C to +125°C

APPLICATIONS

• Graphics Processors

• PC Add-In Cards

• Microprocessors

• Low-Voltage Digital ICs

• High-Efficiency Linear Power Supplies

• Switch-Mode Power-Supply Post Regulation

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Jr S-PAK is a trademark of Texas Instruments Incorporated.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (26 pages)

PAGE 1
TPS740xx SBVS091C – JUNE 2011 – REVISED DECEMBER 2011 www.ti.com 1.5-A, Low-Voltage LDO Regulator with Dual Input Voltages FEATURES DESCRIPTION • • The TPS740xx is a wide bandwidth, very low-dropout, 1.5-A voltage regulator ideal for powering microprocessors. 23 • • • • • • • • • • Small Consumption Current: 3 mA Maximum Input Voltage Range: – VIN: 1.2 V to 6.0 V – VBIAS: 2.9 V to 6.0 V Stable with Any Output Capacitance: ≥ 2.
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TPS740xx SBVS091C – JUNE 2011 – REVISED DECEMBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS740xx SBVS091C – JUNE 2011 – REVISED DECEMBER 2011 www.ti.com THERMAL INFORMATION TPS74001DGK THERMAL METRIC (1) (2) DGK (4 pin short) DPT 8 PINS 5 PINS 136.9 30.0 Junction-to-ambient thermal resistance (4) θJA TPS74001DPT (3) (5) θJCtop Junction-to-case (top) thermal resistance 35.3 15.3 θJB Junction-to-board thermal resistance (6) 68.0 14.4 ψJT Junction-to-top characterization parameter (7) 0.9 0.6 ψJB Junction-to-board characterization parameter (8) 67.8 14.
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TPS740xx SBVS091C – JUNE 2011 – REVISED DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS Over operating temperature range (TJ = –40°C to +125°C), VBIAS = VOUT + 2.0 V, VIN = VOUT + 1 V, COUT = 10 μF, following Recommended Resistor Values, and VEN = 1.1 V, unless otherwise noted. Typical values are at TJ = +25°C. TPS74001 (adjustable output voltage) is tested at VOUT = 0.9 V. TPS740xx PARAMETER TEST CONDITIONS VIN Input voltage range VBIAS Bias pin voltage range MAX UNIT 1.2 TYP 6.0 V 2.9 6.
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TPS740xx SBVS091C – JUNE 2011 – REVISED DECEMBER 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAMS Adjustable Output Voltage Version IN Current Limit BIAS UVLO OUT Thermal Limit VOUT R1 0.9V Reference FB R2 GND Figure 1. Fixed Output Voltage Version IN Current Limit BIAS UVLO OUT Thermal Limit VOUT R1 0.9V Reference EN Hysteresis and Deglitch R2 GND Figure 2.
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TPS740xx SBVS091C – JUNE 2011 – REVISED DECEMBER 2011 www.ti.com PIN CONFIGURATION DPT PACKAGE Jr S-PAK (TOP VIEW) DGK PACKAGE MSOP-8 (TOP VIEW) EN/FB 1 8 GND BIAS 2 7 GND IN 3 6 GND OUT 4 5 GND 1 2 3 4 5 EN/FB BIAS GND IN OUT TAB Table 1. TERMINAL FUNCTIONS TERMINAL DGK (MSOP-8) DPT (Jr S-PAK) EN 1 1 Enable pin; fixed output voltage version only. Driving this pin high enables the regulator; driving this pin low puts the regulator into shutdown mode.
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TPS740xx SBVS091C – JUNE 2011 – REVISED DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS At TJ = +25°C, VIN = 2.5 V, VBIAS = 5.0 V, VOUT(target) = 1.5 V, VEN = VBIAS, CIN = 2.2 μF, CBIAS = 2.2 μF, and COUT = 10 μF, unless otherwise noted. POWER-SUPPLY RIPPLE REJECTION (INPUT SUPPLY) POWER-SUPPLY RIPPLE REJECTION (BIAS SUPPLY) 80 80 70 70 60 60 50 50 PSRR (dB) PSRR (dB) TPS74001 40 VBIAS = 3.3 V VIN = 1.8 V VOUT = 1.0 V IOUT = 1.5 A COUT = 2.2-mF Ceramic 30 20 10 40 VBIAS = 3.3 V VIN = 1.
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TPS740xx SBVS091C – JUNE 2011 – REVISED DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, VIN = 2.5 V, VBIAS = 5.0 V, VOUT(target) = 1.5 V, VEN = VBIAS, CIN = 2.2 μF, CBIAS = 2.2 μF, and COUT = 10 μF, unless otherwise noted. DROPOUT CHARACTERISTICS (INPUT VOLTAGE) 1.6 1.6 VBIAS = 5 V VOUT = 1.5 V 1.4 VIN = 2.5 V VOUT = 1.5 V 1.4 1.2 Output Voltage (V) Output Voltage (V) DROPOUT CHARACTERISTICS (BIAS VOLTAGE) 1 0.8 0.6 0.4 1.2 1 0.8 0.6 0.4 IOUT = 10 mA 0.
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TPS740xx SBVS091C – JUNE 2011 – REVISED DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, VIN = 2.5 V, VBIAS = 5.0 V, VOUT(target) = 1.5 V, VEN = VBIAS, CIN = 2.2 μF, CBIAS = 2.2 μF, and COUT = 10 μF, unless otherwise noted. BIAS CURRENT vs OUTPUT CURRENT 50 VBIAS = 5 V VIN = 2.5 V VOUT = 1.5 V IOUT = 0 mA VIN = 2.5 V VOUT = 1.
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TPS740xx SBVS091C – JUNE 2011 – REVISED DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, VIN = 2.5 V, VBIAS = 5.0 V, VOUT(target) = 1.5 V, VEN = VBIAS, CIN = 2.2 μF, CBIAS = 2.2 μF, and COUT = 10 μF, unless otherwise noted. BIAS CURRENT vs INPUT VOLTAGE REFERENCE VOLTAGE vs INPUT VOLTAGE 0.91 300 VBIAS = 5 V IOUT = 1500 mA Reference Voltage (V) 250 Bias Current (mA) IOUT = 750 mA VBIAS = 5 V VOUT = 1.5 V 200 150 100 0.905 0.9 0.895 50 0.89 0 0 0.5 1 1.5 1.
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TPS740xx SBVS091C – JUNE 2011 – REVISED DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, VIN = 2.5 V, VBIAS = 5.0 V, VOUT(target) = 1.5 V, VEN = VBIAS, CIN = 2.2 μF, CBIAS = 2.2 μF, and COUT = 10 μF, unless otherwise noted. ENABLE THRESHOLD vs TEMPERATURE LOAD TRANSIENT RESPONSE 1.6 Output Voltage (100 mV/div) 1.2 1 0.8 0.6 0.4 0.2 Off VBIAS = 5 V VIN = 2.5 V On Output Current (1 A/div) Enable Threshold (V) 1.4 VBIAS = 3.3 V VIN = 1.8 V VOUT = 1.0 V COUT = 2.
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TPS740xx SBVS091C – JUNE 2011 – REVISED DECEMBER 2011 www.ti.com APPLICATION INFORMATION The TPS740xx belongs to a family of low dropout (LDO) regulators. These regulators use a low-current bias input to power all internal control circuitry, allowing the NMOS-pass transistor to regulate very low input and output voltages. The use of an NMOS-pass FET offers several critical advantages for many applications. Unlike a PMOS topology device, the output capacitor has little effect on loop stability.
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TPS740xx SBVS091C – JUNE 2011 – REVISED DECEMBER 2011 www.ti.com Table 2. Standard 1% Resistor Values for Programming the Output Voltage R1 (kΩ) R2 (kΩ) VOUT (V) Short Open 0.9 0.562 5.11 1.0 0.75 4.53 1.05 1.07 4.99 1.1 1.58 4.75 1.2 1.91 2.87 1.5 2.43 2.43 1.8 3.01 1.69 2.5 4.22 1.58 3.3 5.23 1.74 3.6 INPUT, OUTPUT, AND BIAS CAPACITOR REQUIREMENTS The device is designed to be stable for all available types and values of output capacitors greater than or equal to 2.2 μF.
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TPS740xx SBVS091C – JUNE 2011 – REVISED DECEMBER 2011 www.ti.com DROPOUT VOLTAGE The TPS740xx offers very low dropout performance, making it well-suited for high-current, low VIN/low VOUT applications. The low dropout of the TPS740xx allows the device to be used in place of a dc/dc converter and still achieve good efficiency. This performance provides designers with the power architecture for the application to achieve the smallest, simplest, and lowest cost solution.
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TPS740xx SBVS091C – JUNE 2011 – REVISED DECEMBER 2011 www.ti.com SEQUENCING REQUIREMENTS VIN, VBIAS, and VEN can be sequenced in any order without causing damage to the device. NOTE: current charge greater When VBIAS and VEN are present and VIN is not supplied, this device outputs approximately 50 μA of from OUT.
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TPS740xx SBVS091C – JUNE 2011 – REVISED DECEMBER 2011 www.ti.com LAYOUT RECOMMENDATIONS AND POWER DISSIPATION An optimal layout can greatly improve transient performance, PSRR, and noise. To minimize the voltage drop on the input of the device during load transients, the capacitance on IN and BIAS should be connected as close as possible to the device. This capacitance also minimizes the effects of parasitic inductance and resistance of the input source and can, therefore, improve stability.
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TPS740xx SBVS091C – JUNE 2011 – REVISED DECEMBER 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (November 2011) to Revision C Page • Changed upper voltage in both sub-bullets of second Features bullet ................................................................................ 1 • Changed input supply description in the Description section ......................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 22-Jan-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TPS74001DGKR VSSOP DGK 8 TPS74001DGKT VSSOP DGK TPS74001DPTR VSON DPT TPS74001DPTT VSON TPS74012DGKR TPS74012DGKT SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.4 1.4 8.0 12.0 Q1 2500 330.0 12.4 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 5 2000 330.0 24.4 10.35 11.35 1.2 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 22-Jan-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS74001DGKR VSSOP DGK 8 2500 367.0 367.0 35.0 TPS74001DGKT VSSOP DGK 8 250 210.0 185.0 35.0 TPS74001DPTR VSON DPT 5 2000 367.0 367.0 45.0 TPS74001DPTT VSON DPT 5 250 367.0 367.0 45.0 TPS74012DGKR VSSOP DGK 8 2500 367.0 367.0 35.0 TPS74012DGKT VSSOP DGK 8 250 210.0 185.0 35.
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