Datasheet

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2 Schematic
Figure 1. TPS74001DGK-722 Rev-A Schematic
3 Setup and Board Description
3.1 EVM Input/Output Connectors and Test Jumpers
Table 1. List of Input and Output Connectors
Connector Label Description
J1 BIAS VBIAS input power supply connection: 3 V to 5.5 V. Used to power error amplifier, reference, and
internal control circuits.
J2 GND Return connection for V
BIAS
input power supply.
J3 VIN V
IN
input power supply connection: 1.2 V to 5.5 V.
Note: V
IN
≥ V
OUT
+ V
DO
for proper operation
J4 VOUT Regulated output voltage connection.
J5 GND Return connection for V
IN
input power supply.
J6 GND Return connection for V
OUT
.
JP1 IN/EN/GND Ties EN pin to either V
IN
(high) or GND (low). Used for TPS74012DGK only. Not used for
TPS74001DGK. Driving this pin high enables the regulator. Driving this pin low puts the regulator
into shutdown mode. This pin must not be left unconnected.
3.2 Connection Setup
1. Connect power supply #1 to V
IN
(J3) and its return connection to J5 as shown in Figure 2. V
IN
must be
at least 300 mV (or V
DO
) greater than V
OUT
, up to 5.5 V.
2. Connect power supply #2 to V
BIAS
(J1) and its return connection to J2 as shown in Figure 2. V
BIAS
must
be between 3 V and 5.5 V.
3. An ammeter can be connected in series with either power supply to measure the supply current or bias
current.
4. For TPS74012DGK (fixed voltage part), attach a jumper on JP1, shorting EN and V
IN
(ties EN high).
5. If desired, a load can be connected at the output, J4 and J6.
6. Connect a voltmeter or an oscilloscope voltage probe across the output pins J4 and J6 to observe and
measure the regulated output voltage.
3
SLVU475A–June 2011–Revised June 2011 TPS740xxDGKEVM-722 Evaluation Module
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