Datasheet

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SLVS167C − SEPTEMBER 1998 − REVISED − MAY 1999
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
undervoltage supervisor function
The RESET outputs of the TPS73HD3xx initiate a reset in microcomputer and microprocessor systems in the
event of an undervoltage condition. An internal comparator in the TPS73HD3xx monitors the output voltage of
the regulator to detect the undervoltage condition. When that occurs, the RESET
output transistor turns on,
taking the RESET
signal low.
At programmed output voltages below 1.9 V (on the adjustable regulator only) and on the 1.8 V regulator the
reset function becomes unusable. With a minimum output voltage requirement for a valid RESET
signal (over
temperature) being 1.9 V, RESET
will not operate reliably in this range.
On power up, the output voltage tracks the input voltage. The RESET
output becomes active (low) as V
I
approaches the minimum required for a valid RESET signal (specified at 1.5 V for 25°C and 1.9 V over full
recommended operating temperature range). When the output voltage reaches the appropriate positive-going
input threshold (V
IT+
), a 200-ms (typical) timeout period begins during which the RESET output remains low.
Once the timeout has expired, the RESET
output becomes inactive. Since the RESET output is an open-drain
NMOS, a pullup resistor should be used to ensure that a logic-high signal is indicated.
The supply-voltage-supervisor function is also activated during power down. As the input voltage decays and
after the dropout voltage is reached, the output voltage tracks linearly with the decaying input voltage. When
the output voltage drops below the specified negative-going input threshold (V
IT−
— see electrical
characteristics tables), the RESET
output becomes active (low). It is important to note that if the input voltage
decays below the minimum required for a valid RESET
, the RESET is undefined.
Since the circuit is monitoring the regulator output voltage, the RESET
output can also be triggered by disabling
the regulator or by any fault condition that causes the output to drop below V
IT−
. Examples of fault conditions
include a short circuit on the output and a low input voltage. Once the output voltage is reestablished, either by
reenabling the regulator or removing the fault condition, then the internal timer is initiated, which holds the
RESET
signal active during the 200-ms (typical) timeout period.
Transient loads or line pulses can also cause a reset to occur if proper care is not taken in selecting the input
and output capacitors. Load transients that are faster than 5 µs can cause a reset if high-ESR output capacitors
(greater than approximately 7 Ω) are used. A 1-µs transient causes a reset when using an output capacitor with
greater than 3.5 Ω of ESR. Note that the output-voltage spike during the transient can drop well below the reset
threshold and still not trip if the transient duration is short. A 1-µs transient must drop at least 500 mV below the
threshold before tripping the reset circuit. A 2-µs transient trips RESET
at just 400 mV below the threshold.
Lower-ESR output capacitors help by reducing the drop in output voltage during a transient and should be used
when fast transients are expected.
NOTE:
V
IT+
= V
IT−
+Hysteresis
output noise
The TPS73HD3xx has very low output noise, with a spectral noise density < 2 µV/√Hz. This is important when
noise-susceptible systems, such as audio amplifiers, are powered by the regulator.