Datasheet

Dropout Voltage
Transient Response
dV
dT
+
V
OUT
C
OUT
80kW ø R
LOAD
(4)
dV
dT
+
V
OUT
C
OUT
80kW ø
(
R
1
) R
2
)
ø R
LOAD
(5)
Reverse Current
TPS73719-Q1
TPS73733-Q1
www.ti.com ........................................................................................................................................................................................... SBVS123 – DECEMBER 2008
The TPS737xx uses an NMOS pass transistor to achieve extremely low dropout. When (V
IN
– V
OUT
) is less than
the dropout voltage (V
DO
), the NMOS pass device is in its linear region of operation and the input-to-output
resistance is the R
DS, ON
of the NMOS pass element.
For large step changes in load current, the TPS737xx requires a larger voltage drop from V
IN
to V
OUT
to avoid
degraded transient response. The boundary of this transient dropout region is approximately twice the dc
dropout. Values of V
IN
– V
OUT
above this line ensure normal transient response.
Operating in the transient dropout region can cause an increase in recovery time. The time required to recover
from a load transient is a function of the magnitude of the change in load current rate, the rate of change in load
current, and the available headroom (V
IN
to V
OUT
voltage drop). Under worst-case conditions [full-scale
instantaneous load change with (V
IN
– V
OUT
) close to dc dropout levels], the TPS737xx can take a couple of
hundred microseconds to return to the specified regulation accuracy.
The low open-loop output impedance provided by the NMOS pass element in a voltage follower configuration
allows operation without a 1.0- µ F output capacitor. As with any regulator, the addition of additional capacitance
from the OUT pin to ground reduces undershoot magnitude but increases its duration. In the adjustable version,
the addition of a capacitor, C
FB
, from the OUT pin to the FB pin will also improve the transient response.
The TPS737xx does not have active pulldown when the output is overvoltage. This architecture allows
applications that connect higher voltage sources, such as alternate power supplies, to the output. This
architecture also results in an output overshoot of several percent if the load current quickly drops to zero when a
capacitor is connected to the output. The duration of overshoot can be reduced by adding a load resistor. The
overshoot decays at a rate determined by output capacitor C
OUT
and the internal/external load resistance. The
rate of decay is given by Equation 4 and Equation 5 .
(Fixed voltage version)
(Adjustable voltage version)
The NMOS pass element of the TPS737xx provides inherent protection against current flow from the output of
the regulator to the input when the gate of the pass device is pulled low. To ensure that all charge is removed
from the gate of the pass element, the EN pin must be driven low before the input voltage is removed. If this is
not done, the pass element may be left on because of stored charge on the gate.
After the EN pin is driven low, no bias voltage is needed on any pin for reverse current blocking. Note that
reverse current is specified as the current flowing out of the IN pin because of voltage applied on the OUT pin.
There will be additional current flowing into the OUT pin as a result of the 80-k Ω internal resistor divider to
ground (see Figure 1 and Figure 2 ).
For the TPS73701, reverse current may flow when V
FB
is more than 1.0V above V
IN
.
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