Datasheet

Output Noise
V
N
+ 32mV
RMS
(
R
1
) R
2
)
R
2
+ 32mV
RMS
V
OUT
V
REF
(1)
V
N
ǒ
mV
RMS
Ǔ
+ 27
ǒ
mV
RMS
V
Ǔ
V
OUT
(
V
)
(2)
V V
N RMS
(m )=8.5 (V)x V
OUT
()
mV
RMS
V
(3)
Board Layout Recommendation to Improve PSRR and Noise Performance
Internal Current Limit
Enable Pin and Shutdown
TPS73719-Q1
TPS73733-Q1
SBVS123 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com
A precision bandgap reference is used to generate the internal reference voltage, V
REF
. This reference is the
dominant noise source within the TPS737xx and it generates approximately 32 µ V
RMS
(10 Hz to 100 kHz) at the
reference output (NR). The regulator control loop gains up the reference noise with the same gain as the
reference voltage, so that the noise voltage of the regulator is approximately given by:
Since the value of V
REF
is 1.2V, this relationship reduces to:
for the case of no C
NR
.
An internal 27k Ω resistor in series with the noise reduction pin (NR) forms a low-pass filter for the voltage
reference when an external noise reduction capacitor, C
NR
, is connected from NR to ground. For C
NR
= 10 nF,
the total noise in the 10-Hz to 100-kHz bandwidth is reduced by a factor of ~3.2, giving the approximate
relationship in Equation 3 for C
NR
= 10 nF.
This noise reduction effect is shown as RMS Noise Voltage vs C
NR
in the Typical Characteristics section.
The TPS73701 adjustable version does not have the NR pin available. However, connecting a feedback
capacitor, C
FB
, from the output to the feedback pin (FB) reduces output noise and improve load transient
performance. This capacitor should be limited to 0.1 µ F.
The TPS737xx uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate of
the NMOS pass element above V
OUT
. The charge pump generates ~250 µ V of switching noise at ~4 MHz;
however, charge-pump noise contribution is negligible at the output of the regulator for most values of I
OUT
and
C
OUT
.
To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the
printed circuit board (PCB) be designed with separate ground planes for V
IN
and V
OUT
, with each ground plane
connected only at the GND pin of the device. In addition, the ground connection for the bypass capacitor should
connect directly to the GND pin of the device.
The TPS737xx internal current limit helps protect the regulator during fault conditions. Foldback current limit
helps to protect the regulator from damage during output short-circuit conditions by reducing current limit when
V
OUT
drops below 0.5 V. See Figure 12 in the Typical Characteristics section.
The enable pin (EN) is active high and is compatible with standard TTL-CMOS levels. A V
EN
below 0.5 V (max)
turns the regulator off and drops the GND pin current to approximately 10 nA. When EN is used to shutdown the
regulator, all charge is removed from the pass transistor gate, and the output ramps back up to a regulated V
OUT
(see Figure 23 ).
When shutdown capability is not required, EN can be connected to V
IN
. However, the pass gate may not be
discharged using this configuration, and the pass transistor may be left on (enhanced) for a significant time after
V
IN
has been removed. This scenario can result in reverse current flow (if the IN pin is low impedance) and faster
ramp times upon power-up. In addition, for V
IN
ramp times slower than a few milliseconds, the output may
overshoot upon power-up.
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