Datasheet

V =xV
N OUT
11
V
mV
RMS
TPS735xx
www.ti.com SBVS087K –JUNE 2008–REVISED AUGUST 2013
optimize noise, equivalent series resistance of the As with any linear regulator, PSRR and transient
output capacitor can be set to approximately 0.2Ω. response are degraded as (V
IN
– V
OUT
) approaches
This configuration maximizes phase margin in the dropout. This effect is shown in the Typical
control loop, reducing total output noise by up to Characteristics section.
10%.
Startup and Noise Reduction Capacitor
Noise can be referred to the feedback point (FB pin)
such that with C
NR
= 0.01μF, total noise is given
Fixed voltage versions of the TPS735xx use a quick-
approximately by Equation 1:
start circuit to fast-charge the noise reduction
capacitor, C
NR
, if present (see the Functional Block
Diagrams). This architecture allows the combination
(1)
of very low output noise and fast start-up times. The
The TPS73501 adjustable version does not have the
NR pin is high impedance so a low leakage C
NR
noise-reduction pin available, so ultra-low noise
capacitor must be used; most ceramic capacitors are
operation is not possible. Noise can be minimized
appropriate in this configuration. A high-quality, COG-
according to the above recommendations.
type (NPO) dielectric ceramic capacitor is
recommended for C
NR
when used in environments
Board Layout Recommendations to Improve where abrupt changes in temperature can occur.
PSRR and Noise Performance
Note that for fastest startup, V
IN
should be applied
To improve ac performance such as PSRR, output first, then the enable pin (EN) driven high. If EN is
noise, and transient response, it is recommended that tied to IN, startup is somewhat slower. Refer to the
the board be designed with separate ground planes Typical Characteristics section. The quick-start switch
for V
IN
and V
OUT
, with each ground plane connected is closed for approximately 135μs. To ensure that
only at the GND pin of the device. In addition, the C
NR
is fully charged during the quick-start time, a
ground connection for the bypass capacitor should 0.01μF or smaller capacitor should be used.
connect directly to the GND pin of the device.
Transient Response
Internal Current Limit
As with any regulator, increasing the size of the
The TPS735xx internal current limit helps protect the output capacitor reduces over/undershoot magnitude
regulator during fault conditions. During current limit, but increases duration of the transient response. In
the output sources a fixed amount of current that is the adjustable version, adding C
FB
between OUT and
largely independent of output voltage. For reliable FB improves stability and transient response. The
operation, the device should not be operated in transient response of the TPS735xx is enhanced by
current limit for extended periods of time. an active pull-down that engages when the output
overshoots by approximately 5% or more when the
The PMOS pass element in the TPS735xx has a
device is enabled. When enabled, the pull-down
built-in body diode that conducts current when the
device behaves like a 400Ω resistor to ground.
voltage at OUT exceeds the voltage at IN. This
current is not limited, so if extended reverse voltage
Undervoltage Lock-Out (UVLO)
operation is anticipated, external limiting may be
appropriate.
The TPS735xx utilizes an undervoltage lock-out
circuit to keep the output shut off until internal
Shutdown circuitry is operating properly. The UVLO circuit has a
de-glitch feature so that it typically ignores
The enable pin (EN) is active high and is compatible
undershoot transients on the input if they are less
with standard and low voltage TTL-CMOS levels.
than 50μs duration.
When shutdown capability is not required, EN can be
connected to IN.
Minimum Load
Dropout Voltage The TPS735xx is stable and well-behaved with no
output load. To meet the specified accuracy, a
The TPS735xx uses a PMOS pass transistor to
minimum load of 500μA is required. Below 500μA at
achieve low dropout. When (V
IN
– V
OUT
) is less than
junction temperatures near +125°C, the output can
the dropout voltage (V
DO
), the PMOS pass device is
drift up enough to cause the output pull-down to turn
in its linear region of operation and the input-to-output
on. The output pull-down limits voltage drift to 5%
resistance is the R
DS, ON
of the PMOS pass element.
typically but ground current could increase by
Because the PMOS device behaves like a resistor in
dropout, V
DO
approximately scales with output
current.
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