Datasheet

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at I
O
= 10 mA, EN = 0 V, C
o
= 4.7 µF (CSR
‡
= 1 Ω), SENSE/FB shorted to
OUT (unless otherwise noted)
PARAMETER
TEST CONDITIONS
§
T
J
MIN TYP MAX
UNIT
Ground current (active mode)
EN ≤ 0.5 V
,
V
I
= V
O
+ 1 V
,
25°C 340 400
µA
Gro
u
nd
c
u
rrent
(acti
v
e
mode)
EN
≤
0.5
V,
V
I
V
O
+
1
V,
0 mA ≤ I
O
≤ 500 mA
–40°C to 125°C 550
µ
A
In
p
ut current (standby mode)
EN V
27V≤ V ≤ 10 V
25°C 0.01 0.5
µA
Inp
u
t
c
u
rrent
(standb
y
mode)
EN
=
V
I
,
2
.
7
V
≤
V
I
≤
10
V
–40°C to 125°C 2
µ
A
Out
p
ut current limit
V
O
=0V
V
I
=10V
25°C 1.2 2
A
O
u
tp
u
t
c
u
rrent
limit
V
O
=
0
V
,
V
I
=
10
V
–40°C to 125°C 2
A
Pass-element leakage current in standby
EN V
27V≤ V ≤ 10 V
25°C 0.01 0.5
µA
gy
mode
EN
=
V
I
,
2
.
7
V
≤
V
I
≤
10
V
–40°C to 125°C 1
µ
A
RESET leakage current
Normal operation
V at RESET 10 V
25°C 0.02 0.5
µA
RESET
l
ea
k
age curren
t
N
orma
l
opera
ti
on,
V
a
t
RESET
=
10
V
–40°C to 125°C 0.5
µ
A
Output voltage temperature coefficient –40°C to 125°C 61 75 ppm/°C
Thermal shutdown junction temperature 165 °C
EN logic high (standby mode)
2.5 V ≤ V
I
≤ 6 V
40
°
Cto125
°
C
2
V
EN
l
og
i
c
hi
g
h
(
s
t
an
db
y mo
d
e
)
6 V ≤ V
I
≤ 10 V
–
40°C
to
125°C
2.7
V
EN logic low (active mode)
27V≤ V
I
≤ 10 V
25°C 0.5
V
EN
l
og
i
c
l
ow
(
ac
ti
ve mo
d
e
)
2
.
7
V
≤
V
I
≤
10
V
–40°C to 125°C 0.5
V
EN hysteresis voltage 25°C 50 mV
EN input current
0V≤ V
I
≤ 10 V
25°C –0.5 0.001 0.5
µA
EN
i
npu
t
curren
t
0
V
≤
V
I
≤
10
V
–40°C to 125°C –0.5 0.5
µ
A
Minimum V
I
for active
p
ass element
25°C 2.05 2.5
V
Minim
u
m
V
I
for
acti
v
e
pass
element
–40°C to 125°C 2.5
V
Minimum V
I
for valid RESET
I
O(RESET)
= 300 µA
25°C 1 1.5
V
Mi
n
i
mum
V
I
f
or va
lid
RESET
I
O(RESET)
= –
300
µ
A
–40°C to 125°C 1.9
V
‡
CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any
series resistance added externally, and PWB trace resistance to C
o
.
§
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.