Datasheet

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
The RESET output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event
of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulator
to detect an undervoltage condition on the regulated output voltage.
If that occurs, the RESET output (open-drain NMOS) turns on, taking the RESET signal low. RESET stays low
for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200-ms (typ) time-out
begins. At the completion of the 200-ms delay, RESET
goes high.
An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance
is achieved by replacing the typical pnp pass transistor with a PMOS device.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 35 mV
at an output current of 100 mA for the TPS7350) and is directly proportional to the output current (see Figure 1).
Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is low and remains
constant, independent of output loading (typically 340 µA over the full range of output current, 0 mA to 500 mA).
These two key specifications yield a significant improvement in operating life for battery-powered systems.
The LDO family also features a sleep mode; applying a logic high signal to EN (enable) shuts down the regulator,
reducing the quiescent current to 0.5 µA maximum at T
J
= 25°C.
The TPS73xx is offered in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version
(programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2%
over line, load, and temperature ranges (3% for the 2.5 V and the adjustable version). The TPS73xx family is
available in PDIP (8 pin), SO (8 pin) and TSSOP (20 pin) packages. The TSSOP has a maximum height of
1.2 mm.
Figure 1. Dropout Voltage Versus Output Current
0.25
0.2
0.1
0.05
0
0.15
0 50 100 150 200 250 300
0.3
350 400 450 500
T
A
= 25°C
TPS7348
TPS7350
Dropout Voltage – V
I
O
– Output Current – mA
TPS7333
TPS7330
TPS7325
Figure 2. Typical Application Configuration
†
TPS7325, TPS7330, TPS7333, TPS7348, TPS7350 (fixed-voltage
options)
‡
Capacitor selection is nontrivial. See application information
section for details.
SENSE
RESET
OUT
OUT
9
8
6
10
IN
IN
IN
EN
GND
321
20
15
14
13
V
I
0.1 µF
To System
Reset
CSR = 1 Ω
V
O
10 µF
+
TPS73xxPW
†
C
O
‡
250 kΩ